Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit
yuko.
I am interested in comments on layout/design and if the approach
is bad good etc. and well anything you experienced people can
offer an amateur hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole)
round through via pads are .056" (.020" hole)
square pads bottom .65" x .010"
plcc pads are standard smt

thanks for any advice,
rob
---------------------

robb wrote:

round dip pin through pads are .075" (.029" hole)

They don't look much like 75 thou/mil to me.

Graham

For a hobbies, I would put the Vias outside the IC package area. This way the PLCC will lay flat once you connect the vias
with 30awg wire.

Cheers
"robb" wrote in message ...
Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit
yuko.
I am interested in comments on layout/design and if the approach
is bad good etc. and well anything you experienced people can
offer an amateur hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole)
round through via pads are .056" (.020" hole)
square pads bottom .65" x .010"
plcc pads are standard smt

thanks for any advice,
rob
---------------------

On Fri, 28 Sep 2007 16:28:23 -0400, robb wrote:

Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit yuko.
I am interested in comments on layout/design and if the approach is bad
good etc. and well anything you experienced people can offer an amateur
hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole) round through via pads
are .056" (.020" hole) square pads bottom .65" x .010"
plcc pads are standard smt


Other than moving the vias out from under the chip as Martin suggested,
I only have one suggestion - round the corners a little bit; the inside
can have a hot spot and the sharp corner doesn't really accomplish
anything, but could be a delamination stress point.

Cheers!
Rich

In article ,
"robb" wrote:

Looking for constructive criticism on my plcc/dip adapter ?

For a given board, the copper on it is "free". Plus, the less copper you
are etching off, the faster it gets done. On the "green side" you might
want to look at any pins that are at ground potential, and connect those
to a flood covering most of the board area, rather than etching off most
of the board area. Power also works, and on the red side you might do
ground some places, power other places, to fill in. Often a good idea to
toss in a few capacitors between power and ground while you are at it.

I much prefer oval pads .vs. round - easier to solder to with dip pins.
Other than a rectangular pin 1, I prefer rounded (or 45 degree) corners
on all pads and traces. Anyplace where a fatter trace fits fine, I use a
fatter trace (without cutting trace-to-trace spacing down to a fussy and
hard to work with number).

Some corner of the etch should have a dot or angle mark to tell you how
the PLCC is supposed to mount - either in the space under it, or outside
of it. Same idea and reason as the "different pin 1 convention" you are
following for DIPs - anything that costs essentially nothing and helps
you put it together correctly is a good thing.

If you move the vias out as others suggest, you might fill the middle
under the PLCC - but leave a generous gap to avoid problems with the
contact pads.

--
Cats, coffee, chocolate...vices to live by

On Fri, 28 Sep 2007 16:28:23 -0400, "robb" wrote:

Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit
yuko.
I am interested in comments on layout/design and if the approach
is bad good etc. and well anything you experienced people can
offer an amateur hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole)
round through via pads are .056" (.020" hole)
square pads bottom .65" x .010"
plcc pads are standard smt

thanks for any advice,
rob
---------------------



Looks OK. You might consider making provision for some close-in
power-ground bypass caps, to fixed pins or jumperable, since you'll be
lengthening the plcc leads a lot.

John

robb wrote:

Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit
yuko.
I am interested in comments on layout/design and if the approach
is bad good etc. and well anything you experienced people can
offer an amateur hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole)
round through via pads are .056" (.020" hole)
square pads bottom .65" x .010"
plcc pads are standard smt



I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Also, put unconnected copper markers at the four corners and mark where
pin 1 goes. Helps with alignment. Especially when tired it can easily
happen that a chip is plopped onto it the wrong way (usually followed by
a major expletive).

Oh, and add your name, logo, whatever and if you want to be extra good a
part number for this board plus a blank assembly number field large
enough to write on with a Sharpie.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:

I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.


Graham

On Fri, 28 Sep 2007 16:28:23 -0400, "robb" wrote:

Looking for constructive criticism on my plcc/dip adapter ?

used jpg to keep size down thats why colors/img look a bit
yuko.
I am interested in comments on layout/design and if the approach
is bad good etc. and well anything you experienced people can
offer an amateur hobbyist like myself.

top is red
bottom green

round dip pin through pads are .075" (.029" hole)
round through via pads are .056" (.020" hole)
square pads bottom .65" x .010"
plcc pads are standard smt

thanks for any advice,
rob
---------------------



Here's a similar thing. A 4M sram chip is soldered on top, and it
plugs into an EPROM socket, so we can load and test code during
development. One extra pin picks up the uP /WRITE line, so we can
write to the ram, and one other pin lets us pick up +5 or +3.3 for
power.

All that stuff about stress and angles and teardrops is pretty silly,
at least if you do plated-through holes.

John

"Ecnerwal" wrote in message
...
In article ,
"robb" wrote:

Looking for constructive criticism on my plcc/dip adapter ?

For a given board, the copper on it is "free". Plus, the less
copper you
are etching off, the faster it gets done. On the "green side"
you might
want to look at any pins that are at ground potential, and
connect those
to a flood covering most of the board area, rather than etching
off most
of the board area. Power also works, and on the red side you
might do
ground some places, power other places, to fill in. Often a
good idea to
toss in a few capacitors between power and ground while you are
at it.

Thanks wren lace ,

Is there an operational/safety benefit to flooding empty space
with ground copper ?

and how does one choose the value for the capacitors between
ground and power ? as that is a bit out my scope

thanks for reply and suggestions,
rob

"Rich Grise" wrote in message
news
On Fri, 28 Sep 2007 16:28:23 -0400, robb wrote:

Looking for constructive criticism on my plcc/dip adapter ?

Other than moving the vias out from under the chip as Martin
suggested,
I only have one suggestion - round the corners a little bit;
the inside
can have a hot spot and the sharp corner doesn't really
accomplish
anything, but could be a delamination stress point.

thanks rich
rob

"Joerg" wrote in message
et...
robb wrote:

Looking for constructive criticism on my plcc/dip adapter ?

Oh, and add your name, logo, whatever and if you want to be
extra good a
part number for this board plus a blank assembly number field
large
enough to write on with a Sharpie.

--
Thanks Joerg,
for all the suggestions, i had not even considered the
logo/name/partno but sounds like a good thing to do,

thanks,
rob

"John Larkin" wrote
in message ...
On Fri, 28 Sep 2007 16:28:23 -0400, "robb"
wrote:

Looking for constructive criticism on my plcc/dip adapter ?

Here's a similar thing. A 4M sram chip is soldered on top, and
it
plugs into an EPROM socket, so we can load and test code during
development. One extra pin picks up the uP /WRITE line, so we
can
write to the ram, and one other pin lets us pick up +5 or +3.3
for
power.

All that stuff about stress and angles and teardrops is pretty
silly,
at least if you do plated-through holes.


Thanks John,
for all the help and taking time to paste an example i really
appreciate the suggestions everyone has made.

Probaby no plated through holes this go around, though making a
copper electro-plating tank for through holes sounds like fun.

I have asked other this as well, how do i choose a capacitor
value for the bypass capacitors, and is there a best location to
place this. I also noticed some resitors in your example ? what
purpose do they serve and would i want something similar ?

thanks again for the helpful advice i hope to post a redo
shortly.

One thing i di not quite understand was the point about moving
vias out from under the chip ? seems like alot of unused space
and a great place to dump the vias if you want to keep the
overall package dimensions down ??

thanks again for all the help,
rob

In article ,
"robb" wrote:

Is there an operational/safety benefit to flooding empty space
with ground copper ?

Operationally it can reduce noise pickup and/or radiation. It does
nothing much for safety.

and how does one choose the value for the capacitors between
ground and power ? as that is a bit out my scope

A: what have you got in the junk box - use it.

B: 0.1uF or 0.22 uF are often good values if parts need to be bought.
Place as close to the PLCC power/ground inputs as possible.

When you get into high-speed stuff, I'll defer to the folks that are
doing that - there have been some spirited discussions about bypassing
in the past few months, with adherents of various rules-of-thumb
valiantly proposing myriad "One True Path" options. I was personally
brought up in the 10uF and 0.1uF in parallel rule-of-thumb, but I know
it's a rule-of-thumb, not a religion or "One True Path" or even a set of
values modeled to provide the best possible performance.

For most digital stuff, a 0.1uF from each chip's power to its ground, as
close to the chip as possible, is another rule-of-thumb (for a while you
could get DIP chip sockets which had those built-in for default
power/ground locations for logic - I don't know if they are still
available, less of an issue with SMT parts and the lack of reliability
that sockets provide in the long run. SMT offers the ability to park the
capacitor on the backside of the board right under the chip, which was
"not done" when through hole components were only mounted on one side of
the board, so they could be wave soldered.)

--
Cats, coffee, chocolate...vices to live by

On Sun, 30 Sep 2007 10:15:33 -0400, "robb" wrote:


"John Larkin" wrote
in message ...
On Fri, 28 Sep 2007 16:28:23 -0400, "robb"
wrote:

Looking for constructive criticism on my plcc/dip adapter ?

Here's a similar thing. A 4M sram chip is soldered on top, and
it
plugs into an EPROM socket, so we can load and test code during
development. One extra pin picks up the uP /WRITE line, so we
can
write to the ram, and one other pin lets us pick up +5 or +3.3
for
power.

All that stuff about stress and angles and teardrops is pretty
silly,
at least if you do plated-through holes.


Thanks John,
for all the help and taking time to paste an example i really
appreciate the suggestions everyone has made.

Probaby no plated through holes this go around, though making a
copper electro-plating tank for through holes sounds like fun.

If you don't plate, put big pads on both sides, and solder on both
sides. That will help prevent ripping pads off.

The plating thing is very nasty. Just buy plated-thru boards from a
cheapie proto shop, APCircuits or such.


I have asked other this as well, how do i choose a capacitor
value for the bypass capacitors, and is there a best location to
place this.

0.1 uF ceramic usually works. Further discussion would start a
religious war. Ignore anything else that anyone says.

Place it close to the power pin(s) of the chip, and pour as much
ground as you can, which is what my board does.

I also noticed some resitors in your example ? what
purpose do they serve and would i want something similar ?

Those are zero-ohm jumper sites, so we can power the sram from +5 (the
regular pin) or from the 3.3 volt oddball pin. So far, we've just used
+5, but that may change some day.


thanks again for the helpful advice i hope to post a redo
shortly.

One thing i di not quite understand was the point about moving
vias out from under the chip ? seems like alot of unused space
and a great place to dump the vias if you want to keep the
overall package dimensions down ??

With plated holes, the vias are flat. If you use wire jumper vias, you
have to deal with the solder bumps on top, under the chip, which is
probably no big deal.

What sort of PLCC chips will you be using? What's the overall circuit
going to do?

John

robb wrote:
....

for all the help and taking time to paste an example i really
appreciate the suggestions everyone has made.

Probaby no plated through holes this go around, though making a
copper electro-plating tank for through holes sounds like fun.

Well, it gets old after a while. I used to do all aspects of PCB
manufacture when I worked for a PCB house as a teenager.

The plate through tank is filled with a saturated solution of
copper sulfate. The solution is made by filling the tank with
a sulfuric acid solution, about the same concentration as in a
car battery. The copper anodes are added until the solution stops
eating them away. The plate through tank needs to be highly agitated
to keep the solution in the holes very fresh. So, imagine a tank
full of concentrated sulfuric acid at a roiling boil.

First, you drill all of the holes that are to be plated.

Then you scrub the board so that the copper is free of any oxide,
or fingerprints and give it a bath in a strong lye solution to
remove oils.

The next step is to seed the holes in the board with an electroless
copper plating solution. Metal doesn't like to plate on insulation,
and it really doesn't like to plate in holes, so it needs the thin
copper film to help it start.

Then the boards get clamped firmly to a copper cathode bar, and
get inserted into the copper plating tank. Because the metal doesn't
like to plate into holes, you need to use an excessively high current
density, and high agitation. The tank looks like it is at a roiling
boil. The plating "rectifiers" are 0 to 6V, 300A power supplies.

When the boards are done, the corners will have mossy copper growing
from them, and the surface finish will be uneven, so the board needs
to be sanded down to a nice flat finish. This is done with a brush
machine that does both sides at the same time. Be careful not to
remove too much copper!

Next, the boards get silk screened with resist and go into the
solder plating tank. When they are done there, the silk screen
resist is removed (trichlor was the old way), and they are tossed
into the etching tank, where the solder plating acting as the resist.

After they are rinsed, and dried, they go into a hot bath of
peanut oil where the solder is "reflowed" which basically means
the plating of tin/lead is melted into an actual alloy.

Then comes more trichlor, and the final drilling, and then milling
to shape.

-Chuck

"Chuck Harris" wrote in message


Then the boards get clamped firmly to a copper cathode bar, and
get inserted into the copper plating tank. Because the metal doesn't
like to plate into holes, you need to use an excessively high current
density, and high agitation. The tank looks like it is at a roiling
boil. The plating "rectifiers" are 0 to 6V, 300A power supplies.

In the 80's I once popped out the contents of some holes and they were like
spring coils that fit tightly in the holes. There must have been other
variations.


--

Reply in group, but if emailing add another
zero, and remove the last word.

Tom Del Rosso wrote:
"Chuck Harris" wrote in message

Then the boards get clamped firmly to a copper cathode bar, and
get inserted into the copper plating tank. Because the metal doesn't
like to plate into holes, you need to use an excessively high current
density, and high agitation. The tank looks like it is at a roiling
boil. The plating "rectifiers" are 0 to 6V, 300A power supplies.

In the 80's I once popped out the contents of some holes and they were like
spring coils that fit tightly in the holes. There must have been other
variations.

There were some companies that were incapable of doing plated through
construction that did that, mostly TV and appliance makers. It was
grossly unreliable.

Plated through holes on multilayer holes can look funny because the hole
drilled in the board isn't always perfectly smooth... the boards are
fiberglass laminates, after all and the plating will be an exact image
of all the nooks and crannies in the hole.

-Chuck Harris

"Eeyore" wrote in message
...
PADS IIRC is the only package I've seen that has a teardrop function built
in as
standard.

Pulsonix has teardrop support in any of the configurations that include PCB
support.

Years ago when I was using P-CAD it could do them as well, but it actually
consisted of running a little standalone utility program that added them as
"drawn copper" next to each pad. Hence, you only wanted to do it as the last
step before fabrication! (Whereas Pulsonix and PADS of course both have
teardrops as "native" objects, not just drawn copper.)

On Tue, 02 Oct 2007 06:32:55 -0400, Chuck Harris
wrote:

Tom Del Rosso wrote:
"Chuck Harris" wrote in message

Then the boards get clamped firmly to a copper cathode bar, and
get inserted into the copper plating tank. Because the metal doesn't
like to plate into holes, you need to use an excessively high current
density, and high agitation. The tank looks like it is at a roiling
boil. The plating "rectifiers" are 0 to 6V, 300A power supplies.

In the 80's I once popped out the contents of some holes and they were like
spring coils that fit tightly in the holes. There must have been other
variations.

There were some companies that were incapable of doing plated through
construction that did that, mostly TV and appliance makers. It was
grossly unreliable.

Plated through holes on multilayer holes can look funny because the hole
drilled in the board isn't always perfectly smooth... the boards are
fiberglass laminates, after all and the plating will be an exact image
of all the nooks and crannies in the hole.

-Chuck Harris


How about these PTH's?


John

John Larkin wrote:
On Tue, 02 Oct 2007 06:32:55 -0400, Chuck Harris
wrote:

Tom Del Rosso wrote:
"Chuck Harris" wrote in message

Then the boards get clamped firmly to a copper cathode bar, and
get inserted into the copper plating tank. Because the metal doesn't
like to plate into holes, you need to use an excessively high current
density, and high agitation. The tank looks like it is at a roiling
boil. The plating "rectifiers" are 0 to 6V, 300A power supplies.
In the 80's I once popped out the contents of some holes and they were like
spring coils that fit tightly in the holes. There must have been other
variations.
There were some companies that were incapable of doing plated through
construction that did that, mostly TV and appliance makers. It was
grossly unreliable.

Plated through holes on multilayer holes can look funny because the hole
drilled in the board isn't always perfectly smooth... the boards are
fiberglass laminates, after all and the plating will be an exact image
of all the nooks and crannies in the hole.

-Chuck Harris


How about these PTH's?


John

Those are real beauties!

The plating is always at its thinnest half way through the hole. That is
because the electric currents are lower there than anywhere else on the board,
and the copper needs current to plate out of solution.

I would guess that there was a combination of two problems that caused that PTH
failure. One is not enough plating thickness, and two, a delamination of the
board that caused a gap that the plating had to bridge (unsuccessfully).

Plating being too thin can be caused by 1) too little time, 2) too little current,
3) spent copper anodes, or 4) insufficient agitation.

Chuck

Eeyore wrote:


Joerg wrote:


I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.


Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.


Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.

--
Regards, Joerg

http://www.analogconsultants.com

On Thu, 04 Oct 2007 00:00:26 GMT, Joerg
wrote:

Eeyore wrote:


Joerg wrote:


I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.


Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.


Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Do you think a right-angle trace is more likely to break than a curve
or bevel? I can't see why.

Except maybe for high voltages, or 5+ GHz stuff, I don't think it
matters.

John

John Larkin wrote:
On Thu, 04 Oct 2007 00:00:26 GMT, Joerg

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Do you think a right-angle trace is more likely to break than a curve
or bevel? I can't see why.

A long time ago, the board houses used to warn against right angle traces
because with a solder plate resist they would over etch on the inside of
the right angle. Now days the pitches are so fine that everyone is using
organic resists, for etching, and the insides of right angles under etch
if anything, so it really shouldn't matter.

-Chuck

"John Larkin" ...
Do you think a right-angle trace is more likely to break than a curve
or bevel? I can't see why.

Some time before 1980 I did some PCB layout for the European IRAS satellite.
In those days the minimum inside curvature of a bend was specified (AFAIR
about 0.7 mm inside, mo problem since we taped the layout at 4x or 8x
scale): the reason given was better behaviour with thermal cycling. Outside
had to follow the inside with the track width, no sharp points allowed.

Arie de Muynck.

John Larkin wrote:

On Thu, 04 Oct 2007 00:00:26 GMT, Joerg
wrote:


Eeyore wrote:


Joerg wrote:



I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.


Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.


Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.



Do you think a right-angle trace is more likely to break than a curve
or bevel? I can't see why.


It offers a distinct starting point for a hair crack and as Arie pointed
out is not allowed in some hi-rel designs. This effect is most
pronounced on flex where I never allow right angles. Or any angle for
that matter, it all has to be curved. I have seen too many flex failures
and nearly all boiled down to hair cracks at trace bends or where
tear-drop hadn't been used.


Except maybe for high voltages, or 5+ GHz stuff, I don't think it
matters.


Agree, except for analog stuff where the cutoff can be much lower. In
the digital world a reflection 40dB down makes no difference but in
Radar apps it can matter.

My take on this is, why not do properly rounded traces if there is zero
cost difference and any CAD SW worth its salt can do that automatically?

Strangely, in the olden days folks shunned round traces. Not because CAD
program couldn't do them but because they did not want their design to
look hand-made.

--
Regards, Joerg

http://www.analogconsultants.com

On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:
Eeyore wrote:
Joerg wrote:

I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.

Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)

Cheers!
Rich

John Larkin wrote:

Do you think a right-angle trace is more likely to break than a curve
or bevel? I can't see why.

Concentration of mechanical stress AIUI.

Graham

Rich Grise wrote:

On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:

Eeyore wrote:

Joerg wrote:


I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)


I've always belonged to the group of round-tapers ;-)

--
Regards, Joerg

http://www.analogconsultants.com

On Fri, 05 Oct 2007 18:21:24 GMT, Joerg
wrote:

Rich Grise wrote:

On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:

Eeyore wrote:

Joerg wrote:


I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)


I've always belonged to the group of round-tapers ;-)

I was taught to never bend tape, because longterm it would be under
tension and ooze around on the mylar and change clearances. Ditto to
not make 90 degree bends. So it was

Make 90 deg junction

Overlay diagnonal tape into the corner

Xacto trim, trim, trim, trim.

I sure don't miss manual taping, or slide rules, or typewriters and
carbon paper, or wire-wrap, or thru-hole boards. There's not much I do
miss from the olden days. We are incredibly more productive now.

John

John Larkin wrote:

On Fri, 05 Oct 2007 18:21:24 GMT, Joerg
wrote:


Rich Grise wrote:


On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:


Eeyore wrote:


Joerg wrote:



I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)


I've always belonged to the group of round-tapers ;-)


I was taught to never bend tape, because longterm it would be under
tension and ooze around on the mylar and change clearances. Ditto to
not make 90 degree bends. So it was

Make 90 deg junction

Overlay diagnonal tape into the corner

Xacto trim, trim, trim, trim.


Oh man, we never had to do that. We had Symbol sheets that also came in
a "trace pattern" edition. IIRC it was from a company called LetraSet.
But this was in Europe, no idea if they were for sale here. However,
this stuff was IMHO freaking expensive.


I sure don't miss manual taping, or slide rules, or typewriters and
carbon paper, or wire-wrap, or thru-hole boards. There's not much I do
miss from the olden days. We are incredibly more productive now.


Wire-wrap was IMHO the pits, I never allowed that on any of my designs.
But I helped others a lot finding sub-optimal wraps and stuff. The slide
rule is still frequently used here. Very handy if you want to whip up a
filter from catalog parts or from parts you find in a client's parts bin.

--
Regards, Joerg

http://www.analogconsultants.com

On Sun, 07 Oct 2007 09:28:27 -0700, Joerg
wrote:

John Larkin wrote:

On Fri, 05 Oct 2007 18:21:24 GMT, Joerg
wrote:


Rich Grise wrote:


On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:


Eeyore wrote:


Joerg wrote:



I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)


I've always belonged to the group of round-tapers ;-)


I was taught to never bend tape, because longterm it would be under
tension and ooze around on the mylar and change clearances. Ditto to
not make 90 degree bends. So it was

Make 90 deg junction

Overlay diagnonal tape into the corner

Xacto trim, trim, trim, trim.


Oh man, we never had to do that. We had Symbol sheets that also came in
a "trace pattern" edition. IIRC it was from a company called LetraSet.
But this was in Europe, no idea if they were for sale here. However,
this stuff was IMHO freaking expensive.

Here it was Bishop Graphics. Excellent stuff, but expensive, and now
and then the sales guy would hint that you'd better buy your blueline
supplies from them too, if you wanted your tape and pads to be
delivered. When CAD came along, everybody gave them the finger, and
they're gone.

I don't miss sending art out to be photographed, either. Lorry Ray was
good, though.




I sure don't miss manual taping, or slide rules, or typewriters and
carbon paper, or wire-wrap, or thru-hole boards. There's not much I do
miss from the olden days. We are incredibly more productive now.


Wire-wrap was IMHO the pits, I never allowed that on any of my designs.
But I helped others a lot finding sub-optimal wraps and stuff. The slide
rule is still frequently used here. Very handy if you want to whip up a
filter from catalog parts or from parts you find in a client's parts bin.

I wrote a little LC filter de-normalization program (free for the
asking) that makes it fairly easy. Look up a prototype in Williams,
plug that in, and fiddle with terminations and cutoffs until you
stumble onto a set of values that you can get. Then run LTspice and
see how it will look.

John

John Larkin wrote:

On Sun, 07 Oct 2007 09:28:27 -0700, Joerg
wrote:


John Larkin wrote:


On Fri, 05 Oct 2007 18:21:24 GMT, Joerg
wrote:



Rich Grise wrote:



On Thu, 04 Oct 2007 00:00:26 +0000, Joerg wrote:



Eeyore wrote:



Joerg wrote:




I'll second John's and Rich's comments. Besides rounding you might want
to consider flaring the traces into the pin header vias. I think
layouters call that "drop". That way there could be less stress fractures.

Teardrop. It's astonishing how many good practices of old have been lost as a
result of CAD layout.

There was once a Marconi (Instruments) IIRC guide to pcb layout from the early
days of tape-up. It covered all these subtleties. I've seen excerpts but never
the actual publication.

I HAVE seen foil fractures where a thin trace enters a pad resulting from rough
handling, rework or whatever. Tear drops reduce such stresses hugely. It's basic
engineering.

PADS IIRC is the only package I've seen that has a teardrop function built in as
standard.

Eagle can do that as well AFAIK. But I never do layouts myself.

A lot of layout is common-sense and it gets violated a lot. Why on earth
everyone thinks right angle looks more cool that round traces I will
never understand. And then the stuff breaks.


Right angles are much more "modern" - like chrome-and-glass furniture as
opposed to art deco. ;-)

They're also easier to tape up. ;-)


I've always belonged to the group of round-tapers ;-)


I was taught to never bend tape, because longterm it would be under
tension and ooze around on the mylar and change clearances. Ditto to
not make 90 degree bends. So it was

Make 90 deg junction

Overlay diagnonal tape into the corner

Xacto trim, trim, trim, trim.


Oh man, we never had to do that. We had Symbol sheets that also came in
a "trace pattern" edition. IIRC it was from a company called LetraSet.
But this was in Europe, no idea if they were for sale here. However,
this stuff was IMHO freaking expensive.


Here it was Bishop Graphics. Excellent stuff, but expensive, and now
and then the sales guy would hint that you'd better buy your blueline
supplies from them too, if you wanted your tape and pads to be
delivered. When CAD came along, everybody gave them the finger, and
they're gone.

I don't miss sending art out to be photographed, either. Lorry Ray was
good, though.


I've never seen a LetraSet rep. I bought that stuff via special order
through the book store in town. That company wasn't really specialized
in layouters, they catered more to sign makers. Their letter and symbol
sheets were really handy for creating professionally looking front panels.


I sure don't miss manual taping, or slide rules, or typewriters and
carbon paper, or wire-wrap, or thru-hole boards. There's not much I do
miss from the olden days. We are incredibly more productive now.


Wire-wrap was IMHO the pits, I never allowed that on any of my designs.
But I helped others a lot finding sub-optimal wraps and stuff. The slide
rule is still frequently used here. Very handy if you want to whip up a
filter from catalog parts or from parts you find in a client's parts bin.


I wrote a little LC filter de-normalization program (free for the
asking) that makes it fairly easy. Look up a prototype in Williams,
plug that in, and fiddle with terminations and cutoffs until you
stumble onto a set of values that you can get. Then run LTspice and
see how it will look.


I'd be interested. "jsc AT ieee DOT org" is shorter to type than my biz
email.

I use routines like Aade but mostly just the old slide rule. Goes like
"Ok, we've got 1.2uH, 2.7uH and 4.7uH available here plus the E12 series
for caps, lets see how we can get into the ballpark with that". I am a
bit worried about my Williams, the pages are beginning to turn yellow.

--
Regards, Joerg

http://www.analogconsultants.com

On Sun, 07 Oct 2007 21:14:53 GMT, Joerg
wrote:


I wrote a little LC filter de-normalization program (free for the
asking) that makes it fairly easy. Look up a prototype in Williams,
plug that in, and fiddle with terminations and cutoffs until you
stumble onto a set of values that you can get. Then run LTspice and
see how it will look.


I'd be interested. "jsc AT ieee DOT org" is shorter to type than my biz
email.

I use routines like Aade but mostly just the old slide rule. Goes like
"Ok, we've got 1.2uH, 2.7uH and 4.7uH available here plus the E12 series
for caps, lets see how we can get into the ballpark with that". I am a
bit worried about my Williams, the pages are beginning to turn yellow.

Heck, here it is:

John

John Larkin wrote:

On Sun, 07 Oct 2007 21:14:53 GMT, Joerg
wrote:



I wrote a little LC filter de-normalization program (free for the
asking) that makes it fairly easy. Look up a prototype in Williams,
plug that in, and fiddle with terminations and cutoffs until you
stumble onto a set of values that you can get. Then run LTspice and
see how it will look.


I'd be interested. "jsc AT ieee DOT org" is shorter to type than my biz
email.

I use routines like Aade but mostly just the old slide rule. Goes like
"Ok, we've got 1.2uH, 2.7uH and 4.7uH available here plus the E12 series
for caps, lets see how we can get into the ballpark with that". I am a
bit worried about my Williams, the pages are beginning to turn yellow.


Heck, here it is:

John


Ah, a good old Basic program and under DOS. I wonder why so many people
are dissing Basic. It works and under DOS the execution time seems to be
measurable only in microseconds. No hourglass and stuff like that.

But I won't part with my old slide rule ;-)

--
Regards, Joerg

http://www.analogconsultants.com

But I won't part with my old slide rule ;-)
A few years ago I went for my Amateur Extra Exam. As usual, I had
seriously over prepared. However, I was not prepared for the
collective gasp of the others present when I removed my trusty
Dietzgen from its leather case and placed it on the desk!

I don't think I needed it though...

John Ferrell W8CCW
"Life is easier if you learn to
plow around the stumps"

John Ferrell wrote:

But I won't part with my old slide rule ;-)

A few years ago I went for my Amateur Extra Exam. As usual, I had
seriously over prepared. However, I was not prepared for the
collective gasp of the others present when I removed my trusty
Dietzgen from its leather case and placed it on the desk!


At one company a small but growing group of engineers was gathering
around the lab bench when I came back from getting a bottle of water,
marveling at my slide rule. Then one of them saw me and said "You know,
we may be located in the boonies but we've got electric light and stuff
out here."


I don't think I needed it though...


I still use it. It's the Aristor-Scholar 0903VS

--
Regards, Joerg

http://www.analogconsultants.com

On Mon, 08 Oct 2007 07:52:52 -0700, Joerg
wrote:

John Ferrell wrote:

But I won't part with my old slide rule ;-)

A few years ago I went for my Amateur Extra Exam. As usual, I had
seriously over prepared. However, I was not prepared for the
collective gasp of the others present when I removed my trusty
Dietzgen from its leather case and placed it on the desk!


At one company a small but growing group of engineers was gathering
around the lab bench when I came back from getting a bottle of water,
marveling at my slide rule. Then one of them saw me and said "You know,
we may be located in the boonies but we've got electric light and stuff
out here."

Given target resistance T and starting resistance S, what value P do
we need to put in parallel with S to get T? To 4 places?


t
1/x
p
1/x
-
1/x


which would take a bit longer using a slide rule.

John

"John Larkin" wrote in message
...
Given target resistance T and starting resistance S, what value P do
we need to put in parallel with S to get T? To 4 places?

HP-35S:

T
P
+/-
XEQ P (the parallel resistance program :-) )
ENTER

---Joel
(Who won the HP-35S programming contest at the HHC 2007 conference
recently...)

"Joel Kolstad" wrote in message
...
XEQ P (the parallel resistance program :-) )

^^^ BTW, while everyone knows that the parallel impedance formula is 1/Result
= 1/Z1 + 1/Z2, for those of us who can get geeky with respect to calculators
and numerical methods, using Result = (Z1*Z2)/(Z1+Z2) is more accurate when Z1
is significantly larger or smaller than Z2... hence some of the motivation to
write a program to do it each time.