"John Larkin" wrote
in message ...
On Fri, 28 Sep 2007 16:28:23 -0400, "robb"
wrote:

Looking for constructive criticism on my plcc/dip adapter ?

Here's a similar thing. A 4M sram chip is soldered on top, and
it
plugs into an EPROM socket, so we can load and test code during
development. One extra pin picks up the uP /WRITE line, so we
can
write to the ram, and one other pin lets us pick up +5 or +3.3
for
power.

All that stuff about stress and angles and teardrops is pretty
silly,
at least if you do plated-through holes.


Thanks John,
for all the help and taking time to paste an example i really
appreciate the suggestions everyone has made.

Probaby no plated through holes this go around, though making a
copper electro-plating tank for through holes sounds like fun.

I have asked other this as well, how do i choose a capacitor
value for the bypass capacitors, and is there a best location to
place this. I also noticed some resitors in your example ? what
purpose do they serve and would i want something similar ?

thanks again for the helpful advice i hope to post a redo
shortly.

One thing i di not quite understand was the point about moving
vias out from under the chip ? seems like alot of unused space
and a great place to dump the vias if you want to keep the
overall package dimensions down ??

thanks again for all the help,
rob