Joerg, Why don't you try the attached version?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson a écrit :
Joerg, Why don't you try the attached version?


He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?


--
Thanks,
Fred.

On Mon, 06 Aug 2007 20:12:45 +0200, Fred_Bartoli
wrote:

Jim Thompson a écrit :
Joerg, Why don't you try the attached version?


He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?

I only included those in my schematic since the PSpice model does not.

At these current levels there should be no issue. In fact the very
same clamping occurs in the usual 4060 implementation.

I only object to clamping at currents exceeding ~10mA... latch-up is
risked.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson a écrit :
On Mon, 06 Aug 2007 20:12:45 +0200, Fred_Bartoli
wrote:

Jim Thompson a écrit :
Joerg, Why don't you try the attached version?

He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?

I only included those in my schematic since the PSpice model does not.

At these current levels there should be no issue. In fact the very
same clamping occurs in the usual 4060 implementation.

I only object to clamping at currents exceeding ~10mA... latch-up is
risked.


Yup, but you've the 10nF, you've got rid of the input limiting resistor
and the second inverter is switching fast.
This all depends on the second inverter driving capabilities and looking
at the first graphs on http://focus.ti.com/lit/ds/symlink/cd4060b.pdf
show that this is not impossible.


--
Thanks,
Fred.

Jim Thompson wrote:

Joerg, Why don't you try the attached version?


Thanks, I'll try this after lunch (got to sort out a battery issue right
now).

But in essence that looks just like shorting out the resistor Rs into
the first inverter where all the datasheets say it has to be there and
be two to ten times the timing resistor. ON-Semi excerpt attached.

But I'll give it a shot.

--
Regards, Joerg

http://www.analogconsultants.com

Fred_Bartoli wrote:

Jim Thompson a écrit :

Joerg, Why don't you try the attached version?


He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?


A lot of mixed-signal guys do that. Count me in :-D

As Jim wrote the trick is to guarantee to stay way under the published
latch-up limits. Way, way under. But I have once seen a really brazen
design where someone was feeding a uC through a port pin. Directly from
mains via a drop resistor. The code was obviously "balanced out" so the
power consumption remained somewhat constant. I did not know that and
then my probe accidentally stalled the clock ... POOF!

--
Regards, Joerg

http://www.analogconsultants.com

Jim Thompson wrote:
On Mon, 06 Aug 2007 20:12:45 +0200, Fred_Bartoli
wrote:

Jim Thompson a écrit :
Joerg, Why don't you try the attached version?

He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?

I only included those in my schematic since the PSpice model does not.

At these current levels there should be no issue. In fact the very
same clamping occurs in the usual 4060 implementation.

I only object to clamping at currents exceeding ~10mA... latch-up is
risked.

I thought there was a risk of getting a supply current spike
(amplification of the clamping current) even if the
current didn't get anywhere close to latching. And avoiding
things that add to the supply current is what we are trying
to avoid.

Fred_Bartoli wrote:

Jim Thompson a écrit :

On Mon, 06 Aug 2007 20:12:45 +0200, Fred_Bartoli
wrote:

Jim Thompson a écrit :

Joerg, Why don't you try the attached version?

He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?


I only included those in my schematic since the PSpice model does not.

At these current levels there should be no issue. In fact the very
same clamping occurs in the usual 4060 implementation.

I only object to clamping at currents exceeding ~10mA... latch-up is
risked.


Yup, but you've the 10nF, you've got rid of the input limiting resistor
and the second inverter is switching fast.
This all depends on the second inverter driving capabilities and looking
at the first graphs on http://focus.ti.com/lit/ds/symlink/cd4060b.pdf
show that this is not impossible.


However, the asterisk note under the spec tables says "Data not
applicable to terminal 9 or 10". They should be weaker. How weak is
anyone's guess though and IME app engineering inquiries to that effect
fizzle because those chip design are too old.

--
Regards, Joerg

http://www.analogconsultants.com

Jim Thompson wrote:

Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(

--
Regards, Joerg

http://www.analogconsultants.com

On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:

Jim Thompson wrote:

Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(

Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd

Jon

Jonathan Kirwan wrote:

On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:


Jim Thompson wrote:


Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(


Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd


Thanks, Jon, done that before and it did not help the cross current at all.

--
Regards, Joerg

http://www.analogconsultants.com

On Mon, 06 Aug 2007 20:11:14 GMT, Joerg
wrote:

Jonathan Kirwan wrote:

On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:


Jim Thompson wrote:


Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(


Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd


Thanks, Jon, done that before and it did not help the cross current at all.

Make the left-most 1M into 10K.

Where's the 10pF coming from?

Or, naughty question of the week, Why are you using 4000 series CMOS
in the 21st Century ?:-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

On Mon, 06 Aug 2007 20:11:14 GMT, Joerg
wrote:


Jonathan Kirwan wrote:


On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:



Jim Thompson wrote:



Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(


Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd


Thanks, Jon, done that before and it did not help the cross current at all.


Make the left-most 1M into 10K.


Done that, too. Then it oscillateth no more.


Where's the 10pF coming from?


Don't know but I've tried several caps.


Or, naughty question of the week, Why are you using 4000 series CMOS
in the 21st Century ?:-)


Because it's cheap and does away with the need for regulated VCC. Plus
the functionality of this stuff is so great that some of it was even
ported into other families. For example 74HC4060. But there you can't
have a 3V-18V VCC range anymore.

This design, however, is one that's slated for a port into uC land. The
oscillator in those 4060 devices appears not to be one of the smarter
design in the CD series. Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.

--
Regards, Joerg

http://www.analogconsultants.com

On Mon, 06 Aug 2007 13:58:42 -0700, Joerg
wrote:

Jim Thompson wrote:

On Mon, 06 Aug 2007 20:11:14 GMT, Joerg
wrote:


Jonathan Kirwan wrote:


On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:



Jim Thompson wrote:



Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(


Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd


Thanks, Jon, done that before and it did not help the cross current at all.


Make the left-most 1M into 10K.


Done that, too. Then it oscillateth no more.


Where's the 10pF coming from?


Don't know but I've tried several caps.


Or, naughty question of the week, Why are you using 4000 series CMOS
in the 21st Century ?:-)


Because it's cheap and does away with the need for regulated VCC. Plus
the functionality of this stuff is so great that some of it was even
ported into other families. For example 74HC4060. But there you can't
have a 3V-18V VCC range anymore.

This design, however, is one that's slated for a port into uC land. The
oscillator in those 4060 devices appears not to be one of the smarter
design in the CD series. Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.

Are you making a custom uC? Or just using spare inverters/gates for
your clock?


...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

On Mon, 06 Aug 2007 13:58:42 -0700, Joerg
wrote:


Jim Thompson wrote:


On Mon, 06 Aug 2007 20:11:14 GMT, Joerg
wrote:



Jonathan Kirwan wrote:



On Mon, 06 Aug 2007 19:35:40 GMT, Joerg
wrote:




Jim Thompson wrote:




Joerg, Why don't you try the attached version?


Ok, just did: It chokes, creating humongous bursts of spikes on VCC.
There is no longer a normal oscillation :-(


Can you try it more like this?

||
,---/\/\----+---||------,
| 1M | || 10n |
| | |
| \ |
| / 1M |
| \ |
| | |
| |\ | |\ |
+---| o----+----| o---'
| |/ |/
|
---
--- 10p
|
gnd


Thanks, Jon, done that before and it did not help the cross current at all.


Make the left-most 1M into 10K.


Done that, too. Then it oscillateth no more.



Where's the 10pF coming from?


Don't know but I've tried several caps.



Or, naughty question of the week, Why are you using 4000 series CMOS
in the 21st Century ?:-)


Because it's cheap and does away with the need for regulated VCC. Plus
the functionality of this stuff is so great that some of it was even
ported into other families. For example 74HC4060. But there you can't
have a 3V-18V VCC range anymore.

This design, however, is one that's slated for a port into uC land. The
oscillator in those 4060 devices appears not to be one of the smarter
design in the CD series. Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.


Are you making a custom uC? Or just using spare inverters/gates for
your clock?


The uC would run off its on-chip clock, comes factory calibrated. But I
would need two independent uC because there must be an "Are you still
alive?" check as usually found on mission-critical aircraft systems.

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

[snip]



Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.



There are definitely some quite usable, tame LDOs in existence, and I have
used them. Whether there are two or more providers of them, at a low
enough price, is a more difficult question.


Any particular ones come to mind? I've heard too many times that "with
our socks you can fly to the moon". Initially it worked, then bang, pop,
poof, kablouie. It was like popcorn. Often app engineering was at their
wits end when presented with the evidence.

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


[snip]




Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.



There are definitely some quite usable, tame LDOs in existence, and I
have
used them. Whether there are two or more providers of them, at a low
enough price, is a more difficult question.


Any particular ones come to mind? I've heard too many times that "with
our socks you can fly to the moon". Initially it worked, then bang, pop,
poof, kablouie. It was like popcorn. Often app engineering was at their
wits end when presented with the evidence.


I have never had a problem so far with the ADP3300 and ADP3330, (but watch
out for the different pinouts). I've been using 1uF chip ceramic caps on
input and output. They've been cycled over temperature, however I did not
try putting a step load current into them to check the phase margin, so I
can't say exactly how much phase margin was left. In all cases they just
worked and I didn't worry about it. If I had to make a million devices
using them then I guess I'd look a bit harder, but so far so good.

It was nice being able to use much more of the battery capacity before
dropout, and the error flag is also nice because then I know just when the
battery is too flat.


$0.70, ouch! That deluxe class of regulators is precluded from most of
my designs. It's usually for mass production.

But the AnyCap series from AD is indeed quite good. Just not in my
league from a cost POV :-(

--
Regards, Joerg

http://www.analogconsultants.com

[snip]


Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.


There are definitely some quite usable, tame LDOs in existence, and I have
used them. Whether there are two or more providers of them, at a low
enough price, is a more difficult question.

Chris

Joerg wrote:

Chris Jones wrote:

[snip]



Got to think hard about that porting because I
absolutely will not employ any LDOs in there. No way. Guess I'll be
rolling my own. Again.



There are definitely some quite usable, tame LDOs in existence, and I
have
used them. Whether there are two or more providers of them, at a low
enough price, is a more difficult question.


Any particular ones come to mind? I've heard too many times that "with
our socks you can fly to the moon". Initially it worked, then bang, pop,
poof, kablouie. It was like popcorn. Often app engineering was at their
wits end when presented with the evidence.

I have never had a problem so far with the ADP3300 and ADP3330, (but watch
out for the different pinouts). I've been using 1uF chip ceramic caps on
input and output. They've been cycled over temperature, however I did not
try putting a step load current into them to check the phase margin, so I
can't say exactly how much phase margin was left. In all cases they just
worked and I didn't worry about it. If I had to make a million devices
using them then I guess I'd look a bit harder, but so far so good.

It was nice being able to use much more of the battery capacity before
dropout, and the error flag is also nice because then I know just when the
battery is too flat.

Chris

My preferred oscillator basically is...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

but without the attenuator to avoid the ESD diodes... since my custom
stuff has no ESD diodes on the internal nodes.

Also the inverters are single stage instead of the 3-somes built into
the 74HC04's

U1A, in my designs, is often an NMOS device plus a current source
pull-up, to minimize power consumption.

In a recent RFID tag design, a 2MHz clock runs on 1uA ;-) (1.2V
supply.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

On Mon, 06 Aug 2007 16:35:37 -0700, Jim Thompson
wrote:

My preferred oscillator basically is...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

but without the attenuator to avoid the ESD diodes... since my custom
stuff has no ESD diodes on the internal nodes.

Also the inverters are single stage instead of the 3-somes built into
the 74HC04's

U1A, in my designs, is often an NMOS device plus a current source
pull-up, to minimize power consumption.

In a recent RFID tag design, a 2MHz clock runs on 1uA ;-) (1.2V
supply.)

...Jim Thompson

I forgot to mention... without ESD diodes acting as clamps, this
oscillator is quite insensitive to power supply value. proof is left
as an exercise for the student ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

My preferred oscillator basically is...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

but without the attenuator to avoid the ESD diodes... since my custom
stuff has no ESD diodes on the internal nodes.

Also the inverters are single stage instead of the 3-somes built into
the 74HC04's

U1A, in my designs, is often an NMOS device plus a current source
pull-up, to minimize power consumption.


We hardware dudes must live with what we's gitten in them thar trading
post in Thief River Falls.


In a recent RFID tag design, a 2MHz clock runs on 1uA ;-) (1.2V
supply.)


Yeah, can't get there with discretes. But close. AFAIR my record stands
near 10uA at 13.56MHz.

--
Regards, Joerg

http://www.analogconsultants.com

"Jim Thompson" wrote
in message news
My preferred oscillator basically is...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

That was given as the prefered design in National's "CMOS Oscillators"
appnote in the 1981 4000 book.


but without the attenuator to avoid the ESD diodes... since my custom
stuff has no ESD diodes on the internal nodes.

Can you explain that? No attenuation means you don't get overshoot? That
seems backwards.


Also the inverters are single stage instead of the 3-somes built into
the 74HC04's

My sense is (by intuition but not analysis) that the positive feedback makes
that possible. Right?


--

Reply in group, but if emailing add another
zero, and remove the last word.

On Mon, 6 Aug 2007 22:45:18 -0400, "Tom Del Rosso"
wrote:

"Jim Thompson" wrote
in message news
My preferred oscillator basically is...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

That was given as the prefered design in National's "CMOS Oscillators"
appnote in the 1981 4000 book.


but without the attenuator to avoid the ESD diodes... since my custom
stuff has no ESD diodes on the internal nodes.

Can you explain that? No attenuation means you don't get overshoot? That
seems backwards.

No attenuation means the free end of the capacitor can swing ABOVE and
BELOW rails without clamping.



Also the inverters are single stage instead of the 3-somes built into
the 74HC04's

My sense is (by intuition but not analysis) that the positive feedback makes
that possible. Right?

Yes.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

"Jim Thompson" wrote
in message

but without the attenuator to avoid the ESD diodes... since my
custom stuff has no ESD diodes on the internal nodes.

Can you explain that? No attenuation means you don't get overshoot?
That seems backwards.

No attenuation means the free end of the capacitor can swing ABOVE and
BELOW rails without clamping.

That makes sense. When you said "without the attenuator" it sounded like
you would omit R4 and R5 in a chip design, but that's where you need it
most, where there are no diode clamps.


--

Reply in group, but if emailing add another
zero, and remove the last word.

On Tue, 7 Aug 2007 16:02:26 -0400, "Tom Del Rosso"
wrote:

"Jim Thompson" wrote
in message

but without the attenuator to avoid the ESD diodes... since my
custom stuff has no ESD diodes on the internal nodes.

Can you explain that? No attenuation means you don't get overshoot?
That seems backwards.

No attenuation means the free end of the capacitor can swing ABOVE and
BELOW rails without clamping.

That makes sense. When you said "without the attenuator" it sounded like
you would omit R4 and R5 in a chip design, but that's where you need it
most, where there are no diode clamps.

No. There's no reason you can't go above VDD and below ground with
the gate voltage.

Run the numbers, then you'll see how VDD falls out.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave