Fred_Bartoli wrote:

Jim Thompson a écrit :

On Mon, 06 Aug 2007 20:12:45 +0200, Fred_Bartoli
wrote:

Jim Thompson a écrit :

Joerg, Why don't you try the attached version?

He, he...
Am I dreaming or are you advocating using the ESD diodes for normal
clamping purpose?


I only included those in my schematic since the PSpice model does not.

At these current levels there should be no issue. In fact the very
same clamping occurs in the usual 4060 implementation.

I only object to clamping at currents exceeding ~10mA... latch-up is
risked.


Yup, but you've the 10nF, you've got rid of the input limiting resistor
and the second inverter is switching fast.
This all depends on the second inverter driving capabilities and looking
at the first graphs on http://focus.ti.com/lit/ds/symlink/cd4060b.pdf
show that this is not impossible.


However, the asterisk note under the spec tables says "Data not
applicable to terminal 9 or 10". They should be weaker. How weak is
anyone's guess though and IME app engineering inquiries to that effect
fizzle because those chip design are too old.

--
Regards, Joerg

http://www.analogconsultants.com