This rainy afternoon (East-coasters beware, that usually spells more
snow for you), I was amusing myself trying to behavioral model a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage regulator
for general use, only those inside ASIC's where I can control all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or below VDO.

I'm guessing that output voltage drops linearly with VIN once the
drop-out point is hit??

But what about current capability? Does it drop sharply, linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!

Thanks!

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.

On Sun, 21 Feb 2010 03:13:45 +0530, "pimpom"
wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

On Sat, 20 Feb 2010 13:56:56 -0800, John Larkin
wrote:

On Sun, 21 Feb 2010 03:13:45 +0530, "pimpom"
wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" wrote in
message ...
The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.

LM337? In an earlier thread you noted it also uses an NPN output device.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

On Sat, 20 Feb 2010 15:36:23 -0700, Jim Thompson
wrote:

On Sat, 20 Feb 2010 13:56:56 -0800, John Larkin
wrote:

On Sun, 21 Feb 2010 03:13:45 +0530, "pimpom"
wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.

---
In all fairness, you didn't indicate you were talking about LDO's and
since "dropout voltage" applies to both beasts, who knew?

Glad it got clarified though since, on a rainy Saturday afternoon in
Austin, with nothing better to do than appreciate the difference between
the bottle in front of me and a frontal lobotomy, I was heading for the
soldering iron and the scope...

JF

On Sat, 20 Feb 2010 16:57:41 -0600, John Fields
wrote:

On Sat, 20 Feb 2010 15:36:23 -0700, Jim Thompson
wrote:

On Sat, 20 Feb 2010 13:56:56 -0800, John Larkin
wrote:

On Sun, 21 Feb 2010 03:13:45 +0530, "pimpom"
wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.

---
In all fairness, you didn't indicate you were talking about LDO's and
since "dropout voltage" applies to both beasts, who knew?

Glad it got clarified though since, on a rainy Saturday afternoon in
Austin, with nothing better to do than appreciate the difference between
the bottle in front of me and a frontal lobotomy, I was heading for the
soldering iron and the scope...

JF

I checked the Tequila availability... enchiladas tonight ;-)

I know there are various drop-out behaviors. JL was just trying to be
rude and dismissive with his "Some people (?)".

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" kirjoitti
om...


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.


LP2950 has schematics on datasheet (National version).

-ek

On Sun, 21 Feb 2010 19:11:51 +0200, "E"
wrote:


"Jim Thompson" kirjoitti
viestissä:iro0o5hmfbejuo9lt3udkodidv4nitjd1m@4ax. com...


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.


LP2950 has schematics on datasheet (National version).

-ek


Thanks! I'll check that out. Although my past experiences in the
"jelly bean" business is those schematics are usually "simplified" to
hide IP.

This is getting to be a really amusing mental endeavor! For instance,
how might an LM7805 behave with a zener inserted in its ground lead to
boost the voltage ?:-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 21 Feb 2010 19:11:51 +0200, "E"
wrote:


"Jim Thompson" kirjoitti
viestissä:iro0o5hmfbejuo9lt3udkodidv4nitjd1m@4ax. com...


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.


LP2950 has schematics on datasheet (National version).

-ek


Thanks! Looks good!

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sat, 20 Feb 2010 15:36:23 -0700, Jim Thompson
wrote:

On Sat, 20 Feb 2010 13:56:56 -0800, John Larkin
wrote:

On Sun, 21 Feb 2010 03:13:45 +0530, "pimpom"
wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


The internal schematics of classics like LM317 and LM1117 and such are
on the data sheets. Some people (?) could deduce their behavior from
that.

John

Those aren't LDO's, they're NPN "followers"; not PNP or PMOS, whose
behavior would be radically different, and quite process dependent.

---
In all fairness, you didn't indicate you were talking about LDO's and
since "dropout voltage" applies to both beasts, who knew?

Glad it got clarified though since, on a rainy Saturday afternoon in
Austin, with nothing better to do than appreciate the difference between
the bottle in front of me and a frontal lobotomy, I was heading for the
soldering iron and the scope...

JF

pimpom wrote:
Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


.... and LDOs are real bitches; talk about how to build an oscillator -
just design an amplifier.

On Sun, 21 Feb 2010 00:32:50 -0800, Robert Baer
wrote:

pimpom wrote:
Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


... and LDOs are real bitches; talk about how to build an oscillator -
just design an amplifier.

I'm intent on modeling these suckers accurately enough that
oscillation can be predicted.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells more
snow for you), I was amusing myself trying to behavioral model a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage regulator
for general use, only those inside ASIC's where I can control all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or below VDO.

I'm guessing that output voltage drops linearly with VIN once the
drop-out point is hit??

But what about current capability? Does it drop sharply, linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!

Thanks!

...Jim Thompson

What are your assumptions about the source?
A battery going flat might induce limit-cycle oscillations
that wouldn't show up with a stiff source?? or not...

On Sun, 21 Feb 2010 10:15:31 -0800, mike wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells more
snow for you), I was amusing myself trying to behavioral model a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage regulator
for general use, only those inside ASIC's where I can control all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or below VDO.

I'm guessing that output voltage drops linearly with VIN once the
drop-out point is hit??

But what about current capability? Does it drop sharply, linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!

Thanks!

...Jim Thompson

What are your assumptions about the source?
A battery going flat might induce limit-cycle oscillations
that wouldn't show up with a stiff source?? or not...

From my modeling point of view, the "source" is just "something"
connected to the "IN" terminal.

BUT, The way I am envisioning the model, a flaky source, if you have a
model for it, would induce the very behavior you want to see.

Maybe model "source" as a voltage source with a parameterized
impedance rise?

Or get out a battery manual and model "Charge", a parameter that
reflects both voltage and impedance effects?

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 21 Feb 2010 11:41:49 -0700, Jim Thompson
wrote:

On Sun, 21 Feb 2010 10:15:31 -0800, mike wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells more
snow for you), I was amusing myself trying to behavioral model a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage regulator
for general use, only those inside ASIC's where I can control all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or below VDO.

I'm guessing that output voltage drops linearly with VIN once the
drop-out point is hit??

But what about current capability? Does it drop sharply, linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!

Thanks!

...Jim Thompson

What are your assumptions about the source?
A battery going flat might induce limit-cycle oscillations
that wouldn't show up with a stiff source?? or not...

From my modeling point of view, the "source" is just "something"
connected to the "IN" terminal.

BUT, The way I am envisioning the model, a flaky source, if you have a
model for it, would induce the very behavior you want to see.

Maybe model "source" as a voltage source with a parameterized
impedance rise?

Or get out a battery manual and model "Charge", a parameter that
reflects both voltage and impedance effects?

...Jim Thompson


Overlay multiple un-synched signals to create a psuedo-random average
modulation 'noise' in the drive signal that can be amplitude modulated to
mimic anomalous source events.

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.