I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating point to
the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=

colin wrote:
I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating point to
the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=



nice simulation work!

in real life the vco gain will change with voltage, the divider will
have jitter, and the phase detectors will have crossover distortion..

however, you will be able to achieve most of what you have simulated, it
may require additional filtering and careful parts selection

Marc

"LVMarc" wrote in message
...
colin wrote:
I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating point
to the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=
nice simulation work!

in real life the vco gain will change with voltage, the divider will have
jitter, and the phase detectors will have crossover distortion..

however, you will be able to achieve most of what you have simulated, it
may require additional filtering and careful parts selection

thanks,
well it seems to work better than I had thought,
at least in the sim anyway
wich is the oposite experience of my previos attempts with
other toplogies irl,
so i thought id show it.

the vco il use is 1-2ghz phemt 1/4y stripline with microwave varactors
at each end, it has a wide range but this does mean it has limited
selectivity/Q

jitter probably wont be too bad a problem as the IF and signal will have the
same jitter
and cancel out.

if the prescalers miss a cycle it would upset things a bit,
the real IF will of course be multiplied by the prescale divide ratio.

im not sure if its worth trying to do the PD in ecl so
avoiding the prescalers.

im not sure this can be done with mixers in quite the same way.

I just banged in some values for the loop feedback and it seemed to work ok,
once id got the logic right way round anyway. I usualy have to look in AoE
to do the pll loop maths.

I think the loop bandidth is high enough so any non linearities wont be to
much of a problem,
and cope with the pulling wich is the main problem I was trying to get round
with doing it this way
instead of the n/r digital pll wich do the PD at lowish frequency.

Colin =^.^=

colin wrote:
"LVMarc" wrote in message
...

colin wrote:

I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating point
to the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=

nice simulation work!

in real life the vco gain will change with voltage, the divider will have
jitter, and the phase detectors will have crossover distortion..

however, you will be able to achieve most of what you have simulated, it
may require additional filtering and careful parts selection


thanks,
well it seems to work better than I had thought,
at least in the sim anyway
wich is the oposite experience of my previos attempts with
other toplogies irl,
so i thought id show it.

the vco il use is 1-2ghz phemt 1/4y stripline with microwave varactors
at each end, it has a wide range but this does mean it has limited
selectivity/Q

jitter probably wont be too bad a problem as the IF and signal will have the
same jitter
and cancel out.

if the prescalers miss a cycle it would upset things a bit,
the real IF will of course be multiplied by the prescale divide ratio.

im not sure if its worth trying to do the PD in ecl so
avoiding the prescalers.

im not sure this can be done with mixers in quite the same way.

I just banged in some values for the loop feedback and it seemed to work ok,
once id got the logic right way round anyway. I usualy have to look in AoE
to do the pll loop maths.

I think the loop bandidth is high enough so any non linearities wont be to
much of a problem,
and cope with the pulling wich is the main problem I was trying to get round
with doing it this way
instead of the n/r digital pll wich do the PD at lowish frequency.

Colin =^.^=




Not sure how you use a 1/4 lambda resonator AND get wide band tuning
(2:1) at same time! The 1/4 lambda resonator look 1/2 lambda at twice
the frequency. So the name mus not reflect the exact resonator used.
The its not just a quarter wave at 1 gc resonator?..

What are you building and is this for a commercial endeavor? You may
google search for "Marc Popek" "Patent" RF or VCO or ..other and see
some configurations of first mass produced PLL as crystal bank
replacement, circa 1981!

We found that the long term stability of the reference oscillator
required more time and effort than what was anticipated...

Then electromechanical issues like "Microphoincs" the conversion or wrap
tapping on the case and "hearing" modulation through the receiver chain.

Finally, US FCC and ROW certification measuring and
verficiation/reporting. Always fun and rewarding :-)

Marc Popek

"LVMarc" wrote in message
...
colin wrote:
"LVMarc" wrote in message
...

colin wrote:

I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating
point to the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=

nice simulation work!

in real life the vco gain will change with voltage, the divider will have
jitter, and the phase detectors will have crossover distortion..

however, you will be able to achieve most of what you have simulated, it
may require additional filtering and careful parts selection


thanks,
well it seems to work better than I had thought,
at least in the sim anyway
wich is the oposite experience of my previos attempts with
other toplogies irl,
so i thought id show it.

the vco il use is 1-2ghz phemt 1/4y stripline with microwave varactors
at each end, it has a wide range but this does mean it has limited
selectivity/Q

jitter probably wont be too bad a problem as the IF and signal will have
the same jitter
and cancel out.

if the prescalers miss a cycle it would upset things a bit,
the real IF will of course be multiplied by the prescale divide ratio.

im not sure if its worth trying to do the PD in ecl so
avoiding the prescalers.

im not sure this can be done with mixers in quite the same way.

I just banged in some values for the loop feedback and it seemed to work
ok,
once id got the logic right way round anyway. I usualy have to look in
AoE
to do the pll loop maths.

I think the loop bandidth is high enough so any non linearities wont be
to much of a problem,
and cope with the pulling wich is the main problem I was trying to get
round with doing it this way
instead of the n/r digital pll wich do the PD at lowish frequency.

Colin =^.^=


Not sure how you use a 1/4 lambda resonator AND get wide band tuning (2:1)
at same time! The 1/4 lambda resonator look 1/2 lambda at twice the
frequency. So the name mus not reflect the exact resonator used. The its
not just a quarter wave at 1 gc resonator?..

What are you building and is this for a commercial endeavor? You may
google search for "Marc Popek" "Patent" RF or VCO or ..other and see some
configurations of first mass produced PLL as crystal bank replacement,
circa 1981!

We found that the long term stability of the reference oscillator required
more time and effort than what was anticipated...

Then electromechanical issues like "Microphoincs" the conversion or wrap
tapping on the case and "hearing" modulation through the receiver chain.

Finally, US FCC and ROW certification measuring and
verficiation/reporting. Always fun and rewarding :-)

well its only 1/4y at one frequency,
it acts more like an inductance than a transmision line,
aka stripline inductor perhaps I shld of called it this,
the inductance (wich changes with frequency)
and varactor capcitance determine the frequency.

its just a basic colpits oscillator,
its similar to ones used in sat tv receivers.

the varactors need to have very wide range,
and were hard to find to give 2:1 freq range.

its for a laser range finder, using heterodyne aproach.
hence the need for the offset LO frequency,
an optoelectronic mixer is used wich gives excelent signal to noise ratio
of the received signal.

the phase change varies with frequency by an amount proportional to
distance.

Colin =^.^=