colin wrote:
I knocked up a simulation of my PLL with ramp applied to the
phase error signal to offset the frequency.

there are two phase detectors, each with slope over +/- 180'
used alternately so the phase ramp offset doesnt push the operating point to
the edge
of the slope.

RF vco is ramped from 100-200mhz
and the LO control voltage closely follows this.

The IF looks pretty clean too, even when the ramp resets back to 0v.

ofc real life always has some surprises.

Il be using 2ghz VCOs so il either use an ecl precaler or do they do ecl
gate arrays ?
some cmos gate arrays are pretty fast not sure if any that will togle at
2ghz.

Colin =^.^=



nice simulation work!

in real life the vco gain will change with voltage, the divider will
have jitter, and the phase detectors will have crossover distortion..

however, you will be able to achieve most of what you have simulated, it
may require additional filtering and careful parts selection

Marc