I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."

Thanks,
---Joel

On Wed, 5 Sep 2007 20:58:30 -0700, "Joel Kolstad"
wrote:

I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."

Thanks,
---Joel


Maybe the current limit thingie is glitching?

Professor Larkinergson might be more helpful if you could post a
schematic, too.

John

Joel Kolstad wrote:

I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."


I am not familiar with LT1950 but at first blush it looks like it's
trying to go in and out of continuous current mode (pumping).

Are you using a smoothing inductor at the other side? Could that cause a
resonance? Might want to reduce its value for a test, to see if that's
where the problem is.

--
Regards, Joerg

http://www.analogconsultants.com

On Thu, 06 Sep 2007 08:30:36 -0700, John Larkin
wrote:

On Wed, 5 Sep 2007 20:58:30 -0700, "Joel Kolstad"
wrote:

I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."

Thanks,
---Joel


Maybe the current limit thingie is glitching?

For sure. You usually build-in a delay after snap, so that slew-rate
doesn't turn you back on.


Professor Larkinergson might be more helpful if you could post a
schematic, too.

John

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

On Thu, 06 Sep 2007 08:30:36 -0700, John Larkin
wrote:


On Wed, 5 Sep 2007 20:58:30 -0700, "Joel Kolstad"
wrote:


I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."

Thanks,
---Joel


Maybe the current limit thingie is glitching?


For sure. You usually build-in a delay after snap, so that slew-rate
doesn't turn you back on.


Looks like he's got a p-channel there and the additional turn-on is too
far away for being related to a Cgd spike or other spikes.

--
Regards, Joerg

http://www.analogconsultants.com

"Joerg" wrote in message
...
Are you using a smoothing inductor at the other side?

Yes, and that's actually what I'm going to play with some this morning.

I'll post the schematic here shortly...

---Joel

"John Larkin" wrote in message
...
Maybe the current limit thingie is glitching?

Without filterint it actually tends to glitch *off*, causing the duty cycle to
be too low and the output to fall out of regulation.

Professor Larkinergson might be more helpful if you could post a
schematic, too.

Here you go... it was getting late last night and I didn't want to post this
before cleaning it up a bit!

Thanks for the help, John.

---Joel

Joel Kolstad wrote:

"John Larkin" wrote in message
...

Maybe the current limit thingie is glitching?


Without filterint it actually tends to glitch *off*, causing the duty cycle to
be too low and the output to fall out of regulation.


Professor Larkinergson might be more helpful if you could post a
schematic, too.


Here you go... it was getting late last night and I didn't want to post this
before cleaning it up a bit!

Thanks for the help, John.


Can you post that as PNG or GIF?

--
Regards, Joerg

http://www.analogconsultants.com

For those of you what don't have a copy of LTspice installed, here's a screen
shot of the schematic.

---Joel

"Joerg" wrote in message
t...
Can you post that as PNG or GIF?

I thought of that about 10 seconds after posting the netlist. :-) See the
next message...

---Joel

Joel Kolstad wrote:

For those of you what don't have a copy of LTspice installed, here's a screen
shot of the schematic.


Is C2 really 1000uF? That's a bit highish, I'd reduce that a lot.

Can you hotwire another 100uH across L3, just to watch the effect on the
bench? Probably needs to be larger than 100uH at your low current load
(looks like under 400mA).

Winding L5 may need a lot more turns.

--
Regards, Joerg

http://www.analogconsultants.com

Hello Joerg,

"Joerg" wrote in message
...
Is C2 really 1000uF? That's a bit highish, I'd reduce that a lot.

Yes it is -- it was driven by the ESR, which is 15milliohms (sorry, that
doesn't show up on the schematic by default, but it is modeled by LTspice).

Can you hotwire another 100uH across L3, just to watch the effect on the
bench? Probably needs to be larger than 100uH at your low current load
(looks like under 400mA).

Will do.

Winding L5 may need a lot more turns.

It can only have more turns if L1 and thus L2 end up with more turns. :-)
Well, OK, I suppose in actuality I could get away with another turn and be
OK -- but L1's turns are calculated from trying to run this at 80% duty cycle.

---Joel

Joel Kolstad wrote:

Hello Joerg,

"Joerg" wrote in message
...

Is C2 really 1000uF? That's a bit highish, I'd reduce that a lot.


Yes it is -- it was driven by the ESR, which is 15milliohms (sorry, that
doesn't show up on the schematic by default, but it is modeled by LTspice).


Tantalums? I don't trust them from here to the door frame. Why do you
need such low ESR? BTW regular ceramics are really low as well. That's
what I always use on switchers and I can't recall ever having gone above
10uF.

[...]

--
Regards, Joerg

http://www.analogconsultants.com

Joel Kolstad wrote:

For those of you what don't have a copy of LTspice installed, here's a screen
shot of the schematic.


Just one more remark: That R2/C1 ratio seems unusually high. Typically
one uses at least an order of magnitude less for R (and more for C).
Probably not causing the choking but it may need to be changed.

BTW is the smoke from the Plumas County fire now heading into your
direction? Yesterday it was quite nasty here, lots of coughing. Even
today it's still smokey and the sun is an eerie orange.

--
Regards, Joerg

http://www.analogconsultants.com

Hi Harry,

"Harry Dellamano" wrote in message
...
Looking at the pics of the current ramp you can see that it is turning off
at two different voltage levels, 38mV and 50mV every other cycle.

I believe it only turns off at 38mV because the IC has a maximum duty cycle
clamp that (if you don't mess with the Vsrc pin, as I haven't on the PCB yet)
always terminates cycles at ~95%.

The error amp output is oscillating at Fo/2 or sub-harmonic oscillation. It
is very difficult to get 65% duty no matter how much slope comp you have.
Change the turns ratio for max duty at 60%.

OK... I'm playing with output inductors at the moment, but I'll try that in a
bit if I don't make any headway.

Looks like the reset winding may not be necessary.

Agreed -- I was actually a little surprised about that!

---Joel

"Joerg" wrote in message
t...
Tantalums?

Nope, electrolytics... the high-quality Panasonic variety.

I don't trust them from here to the door frame. Why do you need such low
ESR?

Well... it's a combination of getting an electrolytic cap that'll handle the
ripple current, and that usually drives you to a pretty low ESR and hence
high-capacitance capacitor anyway as well as supplying current to the load
(which steps between 0 and 1A) while the switcher "catches up." Minimizing
ripple is also always good (this is really the same thing as handling the RMS
current, though, since AFAIK the idea is that self-heating is due to the ESR
and therefore ESR is directly proportional to ripple current handling
capabilities). Having

BTW regular ceramics are really low as well. That's what I always use on
switchers and I can't recall ever having gone above 10uF.

If you keep the ESR the same (15mOhm) and change the output capacitor to 10uF,
in my simulation you end up with a little more than 2V of ripple... ouch! :-)

---Joel

I've been playing around today, and here's what I've found:

-- The output inductor doesn't make much difference. Making it smaller (I
went down to ~10uH -- too small! -- after initially stepping from 100uH to
50uH) results in everything being clearly discontinuous/faster current
ramping, as one would expect. Making it bigger (I went up to 250uH)
eventually results in the continuous operation, of course... but the FET's
gate switching doesn't change. I did find one "magic inductor" that actually
"fixed" the problem except at input voltages =3.1V, but I think it's just
coincidence. The magic inductor happened to have been 39uH and wound on a
bobbin, which I tend to dislike relative to a toroid since of course it sprays
flux around everywhere.

-- I took Harry's suggestion and ran the thing open loop, just applying a
fixed control voltage to the part's "Comp" pin (this voltage is "nominally"
1-2.5V and controls the current trip setpoint). This is where things got
interesting... up until ~2.3V (which gets you close to 65% duty cycle),
everything was fine... but at 2.32V, I get the infamous short cycle/long cycle
behavior (which I'm now referring to as "stuttering"). See the attached
graphic -- upper drive is gate drive, lower trace is output inductor current.
Upon closer inspection, what's really happening is that you get one 11us cycle
followed by a 9us cycle. At 100kHz all cycles *should* be 10us, and for the
life of me I can't imagine how the internal oscillator would alternate between
two periods. The block diagram of the LT1950 shows the oscillator's output
going directly to the "set" output of the gate drive flip-flop (I did ground
the "Sync" input pin for good measure, even though the data sheet says it's OK
to leave it floating).

So that's it... it's not really two different duty cycles per se, it's a
stuttering clock. This is most bizarre, and I'm really beginning to think the
chip might be a little buggy. Anyone have any guesses as to what could cause
this?

It would appear that the solution (workaround, really) is to take Harry's
suggestion and just design it to not require a duty cycle greater than 60%.
grumble, efficiency dropping, grumble .

I've forwarded all this information to Linear Tech as well... I want to
believe I'm at the point where I'm not just wasting some FAE's time due to
having to ask too many newbie questions. :-)

---Joel

Joel Kolstad wrote:

I've been playing around today, and here's what I've found:

-- The output inductor doesn't make much difference. Making it smaller (I
went down to ~10uH -- too small! -- after initially stepping from 100uH to
50uH) results in everything being clearly discontinuous/faster current
ramping, as one would expect. Making it bigger (I went up to 250uH)
eventually results in the continuous operation, of course... but the FET's
gate switching doesn't change. I did find one "magic inductor" that actually
"fixed" the problem except at input voltages =3.1V, but I think it's just
coincidence. The magic inductor happened to have been 39uH and wound on a
bobbin, which I tend to dislike relative to a toroid since of course it sprays
flux around everywhere.

-- I took Harry's suggestion and ran the thing open loop, just applying a
fixed control voltage to the part's "Comp" pin (this voltage is "nominally"
1-2.5V and controls the current trip setpoint). This is where things got
interesting... up until ~2.3V (which gets you close to 65% duty cycle),
everything was fine... but at 2.32V, I get the infamous short cycle/long cycle
behavior (which I'm now referring to as "stuttering"). See the attached
graphic -- upper drive is gate drive, lower trace is output inductor current.
Upon closer inspection, what's really happening is that you get one 11us cycle
followed by a 9us cycle. At 100kHz all cycles *should* be 10us, and for the
life of me I can't imagine how the internal oscillator would alternate between
two periods. The block diagram of the LT1950 shows the oscillator's output
going directly to the "set" output of the gate drive flip-flop (I did ground
the "Sync" input pin for good measure, even though the data sheet says it's OK
to leave it floating).

So that's it... it's not really two different duty cycles per se, it's a
stuttering clock. This is most bizarre, and I'm really beginning to think the
chip might be a little buggy. Anyone have any guesses as to what could cause
this?

It would appear that the solution (workaround, really) is to take Harry's
suggestion and just design it to not require a duty cycle greater than 60%.
grumble, efficiency dropping, grumble .


That is a good suggestion I think. I've had to use duty cycles in excess
of 90% and it is no fun.


I've forwarded all this information to Linear Tech as well... I want to
believe I'm at the point where I'm not just wasting some FAE's time due to
having to ask too many newbie questions. :-)


As Harry mentioned check that negative going peak on the FET drive. I
don't particularly like gate resistors but you might need 22ohms or such
if the chip can't stomach this.

Also, probe around all the pins of the chip to see if there is anything
suspicious. Take a look at R2/C1. R2 is way too high IMHO. Hi-Z nodes
are no fun in switchers, one wee spike getting in there can throw things
off the rocker. It could be a spike so small that the DSO can't really
see it.

BTW I'd do those measurements with an analog scope such as a Tek 2465.
It will show much more information. For example, I once had a switcher
where somehow line frequency got in and modulated the PWM. On the DSO it
looked like a Harley with bad spark plugs but an old Tek 7000 clearly
showed the modulation.

--
Regards, Joerg

http://www.analogconsultants.com

Joel Kolstad wrote:

"Joerg" wrote in message
t...

Tantalums?


Nope, electrolytics... the high-quality Panasonic variety.


I don't trust them from here to the door frame. Why do you need such low
ESR?


Well... it's a combination of getting an electrolytic cap that'll handle the
ripple current, and that usually drives you to a pretty low ESR and hence
high-capacitance capacitor anyway as well as supplying current to the load
(which steps between 0 and 1A) while the switcher "catches up." Minimizing
ripple is also always good (this is really the same thing as handling the RMS
current, though, since AFAIK the idea is that self-heating is due to the ESR
and therefore ESR is directly proportional to ripple current handling
capabilities). Having


How long does it need to catch up? Should be in the sub-msec range.


BTW regular ceramics are really low as well. That's what I always use on
switchers and I can't recall ever having gone above 10uF.


If you keep the ESR the same (15mOhm) and change the output capacitor to 10uF,
in my simulation you end up with a little more than 2V of ripple... ouch! :-)


That looks like the switcher seriously runs out of steam at 1A. Ideally
it should be designed so it can supply the highest peak ever expected.
Then the cap should not need to be that large. Have you tried to run it
at 1A continuous?

--
Regards, Joerg

http://www.analogconsultants.com

On Wed, 5 Sep 2007 20:58:30 -0700, "Joel Kolstad"
wrote:

I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."


Just love simulation.......

Try sticking 5nH in series with your sense resistor. It's awfull hard
getting wide bandwidth at this impedance level. (Try the same in
series with some of the IC pins...just joking).

The simulation will show that the first microsecond or so at the IC
sense pin still has a negative slope, so you can't pwm on it.

When the simulation shows the sensing waveform to be adequately
filtered, you might expect the component values to work in real life,
without a scope probe attached.

Increasing slope compensation isn't normally expected to produce
subharmonics, per your note, but I suppose there's a practal limit to
normal oscillator's internal function.

RL

Hi Harry,

"Harry Dellamano" wrote in message
...
I see your gate output bottoming at -.85V so the substrate is forward biased
and changing your clock period. Get a Schotkey diode and clamp to ground at
the gate output. May help.

Aha! Thanks, Harry, that's definitely improved the situation a lot.
Open-loop, I can still get it to misbehave at the extremes of the error
voltage, but it doesn't go through "working - not working - working - not
working..." as the error voltage increases like it did without the diode.
This makes the entire thing work except for a few corner cases, right as
you're pushing 80% duty cycle (where it still "stutters"). Even open-loop the
duty cycle gets very jittery and non-linear with respect to error voltage
right around 65% duty cycle, so tomorrow I'll go ahead and wind another
transformer based on a 60% maximum D.C. as you suggested -- the LT1950 seems
to be trying to tell me it would prefer that, no?

---Joel

Good evening Joerg,

"Joerg" wrote in message
...
As Harry mentioned check that negative going peak on the FET drive. I don't
particularly like gate resistors but you might need 22ohms or such if the
chip can't stomach this.

The Schottky diode Harry suggested appears to have made it happy. I tried a
4.7 ohm gate resistor as well, and it didn't make a difference.

I'm thinking the source of the negative voltage on the gate drive pin is...
capacitve coupling from a negative spike on the drain from leakage inductance
in the primary?

Also, probe around all the pins of the chip to see if there is anything
suspicious.

The rest looked OK, although I'd have to admit it was with a digital scope --
I'll haul out the 2465 tomorrow and check again for good measure.

Take a look at R2/C1. R2 is way too high IMHO.

Agreed; it's actually changed to 150k/1nF at the moment. Tomorrow -- if
things go well -- I'll drop the capacitors and re-compute the compensation
network, which off-the-cuff I believe will reduce R1/increase C1 without
unduly restricting frequency response.

---Joel

Joerg,

I started looking at capacitors again to figure out just why they were chosen
so high, and it's apparent to me now that it was driven by priorities in the
following order:

1) Lifetime -- the longer, the better (this project has absurd temperature
extremes, and after you choose a particular "line" of capacitors, it seems
that it's pretty much case size alone that determines life... the 1000uF caps
I'm using are 7000 hours rated @ 105C, and I really sort of wish I could find
comparable 10000 hour units.)
2) ESR
3) Capacitance
4) Price :-)

So... I'll keep looking... so far I haven't found anything that comes close to
7000 hours while still maintaining a decent (100mOhm, say) ESR.

---Joel

Joerg,

I started looking at capacitors again to figure out just why they were
chosen so high, and it's apparent to me now that it was driven by
priorities in the following order:

1) Lifetime -- the longer, the better (this project has absurd
temperature extremes, and after you choose a particular "line" of
capacitors, it seems that it's pretty much case size alone that
determines life... the 1000uF caps I'm using are 7000 hours rated @
105C, and I really sort of wish I could find comparable 10000 hour
units.)
2) ESR
3) Capacitance
4) Price :-)

So... I'll keep looking... so far I haven't found anything that comes
close to 7000 hours while still maintaining a decent (100mOhm, say)
ESR.


Have a look at Sanyo OSCONs.


---Joel

Joel Kolstad wrote:

Good evening Joerg,

"Joerg" wrote in message
...

As Harry mentioned check that negative going peak on the FET drive. I don't
particularly like gate resistors but you might need 22ohms or such if the
chip can't stomach this.


The Schottky diode Harry suggested appears to have made it happy. I tried a
4.7 ohm gate resistor as well, and it didn't make a difference.


Quite suspicious if an IC misfires because it's outputs are tortured a
bit. Not s'posed to happen, IMHO. This is one reason I rarely use PWM
chips in switchers. Had a similar thing with a stepper driver IC at a
client, kicked them all out.

4.7ohm ain't much. It would need to be higher.


I'm thinking the source of the negative voltage on the gate drive pin is...
capacitve coupling from a negative spike on the drain from leakage inductance
in the primary?


Cgd is what couples back. But it's only a real issue for HV apps, where
the drain has to switch tens of volts. On 15V max this shouldn't cause a
problem in a PWM driver. After all, it is supposed to live with real
world conditions. One of the few PWM chips I did use is the LM3478 and
it had no problem with this and in my case the drain had to muscle 100V
around.


Also, probe around all the pins of the chip to see if there is anything
suspicious.


The rest looked OK, although I'd have to admit it was with a digital scope --
I'll haul out the 2465 tomorrow and check again for good measure.


Take a look at R2/C1. R2 is way too high IMHO.


Agreed; it's actually changed to 150k/1nF at the moment. Tomorrow -- if
things go well -- I'll drop the capacitors and re-compute the compensation
network, which off-the-cuff I believe will reduce R1/increase C1 without
unduly restricting frequency response.


--
Regards, Joerg

http://www.analogconsultants.com

Joel Kolstad wrote:

Joerg,

I started looking at capacitors again to figure out just why they were chosen
so high, and it's apparent to me now that it was driven by priorities in the
following order:

1) Lifetime -- the longer, the better (this project has absurd temperature
extremes, and after you choose a particular "line" of capacitors, it seems
that it's pretty much case size alone that determines life... the 1000uF caps
I'm using are 7000 hours rated @ 105C, and I really sort of wish I could find
comparable 10000 hour units.)
2) ESR
3) Capacitance
4) Price :-)

So... I'll keep looking... so far I haven't found anything that comes close to
7000 hours while still maintaining a decent (100mOhm, say) ESR.


Absurd temp extremes and electrolytics don't mix well. I'd still look
into figuring out why it isn't able to catch up upon a jump to 1A.

--
Regards, Joerg

http://www.analogconsultants.com

After getting this converter working pretty well last week, I have a short
week so I need to worry about some software and other items. However, the
Linear Tech FAE finally got back to me today via e-mail, and while he didn't
bother to answer or speculate why the chip would generate an 11us cycle
followed by a 9us cycle, he did "recommend" that, since the output isn't
isolated, a "simple boost converter" would be a better choice of topology.

OK, in my mind, a 3V input, 14.7V output, 15W boost converter is going to
require one pretty honkin' huge inductor to get reasonable losses at the very
large magnetizing current (probably 20+ amps) it's going to have support. I
told him this, but of course I'm not about to turn down someone else's free
design work if he manages to make it work. :-)

Thoughts?

---Joel