On Thu, 06 Sep 2007 08:30:36 -0700, John Larkin
wrote:

On Wed, 5 Sep 2007 20:58:30 -0700, "Joel Kolstad"
wrote:

I have this LT1950-based current-mode forward converter that I've designed,
simulated, and built (I can post the LTspice file if anyone wants it). In
simulation everything was reasonably easy to get working, whereas on a real
PCB here it's turning out to be somewhat more difficult. At the moment I'm
finding that the converter appears to use two cycles -- one at the IC's
maximum duty cycle of ~95% and the other with a duty cycle of ~65%. This
averages out to a duty cycle of ~80%, which is correct (and what I see in
simulation). I've included two scope shots below... the first shows the gate
driver signal (bottom, green) as well as the FET's source node (top, yellow).
The second shot shows the current through the FET. The output voltage *does*
remain regulated.

Any idea why it's "choosing" to behave this way rather than the way it
"should?" I've played around with the slope compensation without luck
(there's no improvement until the point there's so much extra compensation
that the load gets starved for current and falls out of regulation) as well as
the loop compensation (it doesn't really seem to matter much).

I'm hoping one of you will be able to say, "Ah, that's classic Larkinergson
sub-harmonic oscillation! Read up on it in Jim's paper here..."

Thanks,
---Joel


Maybe the current limit thingie is glitching?

For sure. You usually build-in a delay after snap, so that slew-rate
doesn't turn you back on.


Professor Larkinergson might be more helpful if you could post a
schematic, too.

John

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave