Joel Kolstad wrote:

I've been playing around today, and here's what I've found:

-- The output inductor doesn't make much difference. Making it smaller (I
went down to ~10uH -- too small! -- after initially stepping from 100uH to
50uH) results in everything being clearly discontinuous/faster current
ramping, as one would expect. Making it bigger (I went up to 250uH)
eventually results in the continuous operation, of course... but the FET's
gate switching doesn't change. I did find one "magic inductor" that actually
"fixed" the problem except at input voltages =3.1V, but I think it's just
coincidence. The magic inductor happened to have been 39uH and wound on a
bobbin, which I tend to dislike relative to a toroid since of course it sprays
flux around everywhere.

-- I took Harry's suggestion and ran the thing open loop, just applying a
fixed control voltage to the part's "Comp" pin (this voltage is "nominally"
1-2.5V and controls the current trip setpoint). This is where things got
interesting... up until ~2.3V (which gets you close to 65% duty cycle),
everything was fine... but at 2.32V, I get the infamous short cycle/long cycle
behavior (which I'm now referring to as "stuttering"). See the attached
graphic -- upper drive is gate drive, lower trace is output inductor current.
Upon closer inspection, what's really happening is that you get one 11us cycle
followed by a 9us cycle. At 100kHz all cycles *should* be 10us, and for the
life of me I can't imagine how the internal oscillator would alternate between
two periods. The block diagram of the LT1950 shows the oscillator's output
going directly to the "set" output of the gate drive flip-flop (I did ground
the "Sync" input pin for good measure, even though the data sheet says it's OK
to leave it floating).

So that's it... it's not really two different duty cycles per se, it's a
stuttering clock. This is most bizarre, and I'm really beginning to think the
chip might be a little buggy. Anyone have any guesses as to what could cause
this?

It would appear that the solution (workaround, really) is to take Harry's
suggestion and just design it to not require a duty cycle greater than 60%.
grumble, efficiency dropping, grumble .


That is a good suggestion I think. I've had to use duty cycles in excess
of 90% and it is no fun.


I've forwarded all this information to Linear Tech as well... I want to
believe I'm at the point where I'm not just wasting some FAE's time due to
having to ask too many newbie questions. :-)


As Harry mentioned check that negative going peak on the FET drive. I
don't particularly like gate resistors but you might need 22ohms or such
if the chip can't stomach this.

Also, probe around all the pins of the chip to see if there is anything
suspicious. Take a look at R2/C1. R2 is way too high IMHO. Hi-Z nodes
are no fun in switchers, one wee spike getting in there can throw things
off the rocker. It could be a spike so small that the DSO can't really
see it.

BTW I'd do those measurements with an analog scope such as a Tek 2465.
It will show much more information. For example, I once had a switcher
where somehow line frequency got in and modulated the PWM. On the DSO it
looked like a Harley with bad spark plugs but an old Tek 7000 clearly
showed the modulation.

--
Regards, Joerg

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