I am trying to divide a 2048 Hz clock pulse to 10.5Hz. Based on info
obtained so far, I have a CD4040 wired as follows to make the divisors
additive.

Clock into pin 10. Diodes connected to pins 9, 7, 4 and 13. The anodes
all go to reset pin 11. Pin 11 has a 1M pull-up to Vdd. According to
the data sheet, the corresponding divisors are 1, 2, 64 and 128. That
ads to 195. 2048/195=10.5, or so it would seem.

There is a nice squarewave on the scope. However, the frequency
reading at the most significant digit output (pin 13) is 16Hz.

Can someone please tell me what I am missing here?

Kevin Brooks

"Kevin Brooks" schreef in bericht
...
I am trying to divide a 2048 Hz clock pulse to 10.5Hz. Based on info
obtained so far, I have a CD4040 wired as follows to make the divisors
additive.

Clock into pin 10. Diodes connected to pins 9, 7, 4 and 13. The anodes
all go to reset pin 11. Pin 11 has a 1M pull-up to Vdd. According to
the data sheet, the corresponding divisors are 1, 2, 64 and 128. That
ads to 195. 2048/195=10.5, or so it would seem.

There is a nice squarewave on the scope. However, the frequency
reading at the most significant digit output (pin 13) is 16Hz.

Can someone please tell me what I am missing here?

Kevin Brooks



You're missing some knowledge. That CD4040 is a ripple counter, that's to
say the output of a stage serves as a clock for the next stage. The delay is
lang enough to have false overall outputs between a clockpuls entering the
first stage and the effect of that pulse in the last stage. As it's a dirty
way of designing anyway, you can't make it worse by adding some delay in the
reset circuit. So lower the 1M pullup to let's say 10k and add a capacitor
of 100p between that resistor and the ground. If that's not enough you can
lower the resistor and raise the capacitor value until you achive the result
you want.

petrus bitbyter

On Wed, 21 Mar 2007 09:46:01 +1100, Kevin Brooks
wrote:

I am trying to divide a 2048 Hz clock pulse to 10.5Hz. Based on info
obtained so far, I have a CD4040 wired as follows to make the divisors
additive.

Clock into pin 10. Diodes connected to pins 9, 7, 4 and 13. The anodes
all go to reset pin 11. Pin 11 has a 1M pull-up to Vdd. According to
the data sheet, the corresponding divisors are 1, 2, 64 and 128. That
ads to 195. 2048/195=10.5, or so it would seem.

There is a nice squarewave on the scope. However, the frequency
reading at the most significant digit output (pin 13) is 16Hz.

Can someone please tell me what I am missing here?

---
Are you sure you're pulling pin 11 high? MR is positive true and
with the diode cathodes also connected to pin 11 there's no way MR
could ever go low and let the counter count..


--
JF

Below is linked the circuit as you have kindly suggested. I am still
not getting a 10.5Hz squarewave from pin 13. Have tried varying the RC
values to no avail.

The other outputs have irregular pulse widths at strange frequencies
as well, none of which correspond to the maths of adding the divisors.

http://home.iprimus.com.au/loungecinema/cd4040.gif

I garther from your previous comments this is an untidy design
approach. Is it, in fact, a lost cause? What is the best solution for
a progammable divide by N? I am trying to keep chip count down.

I saw another design that ran the reset through a 74HC74. Would that
help?

I know about the CD4059 but prefer not to go BCD.

Many thanks,

Kevin Brooks


On Wed, 21 Mar 2007 00:52:01 +0100, "petrus bitbyter"
wrote:


"Kevin Brooks" schreef in bericht
.. .
I am trying to divide a 2048 Hz clock pulse to 10.5Hz. Based on info
obtained so far, I have a CD4040 wired as follows to make the divisors
additive.

Clock into pin 10. Diodes connected to pins 9, 7, 4 and 13. The anodes
all go to reset pin 11. Pin 11 has a 1M pull-up to Vdd. According to
the data sheet, the corresponding divisors are 1, 2, 64 and 128. That
ads to 195. 2048/195=10.5, or so it would seem.

There is a nice squarewave on the scope. However, the frequency
reading at the most significant digit output (pin 13) is 16Hz.

Can someone please tell me what I am missing here?

Kevin Brooks



You're missing some knowledge. That CD4040 is a ripple counter, that's to
say the output of a stage serves as a clock for the next stage. The delay is
lang enough to have false overall outputs between a clockpuls entering the
first stage and the effect of that pulse in the last stage. As it's a dirty
way of designing anyway, you can't make it worse by adding some delay in the
reset circuit. So lower the 1M pullup to let's say 10k and add a capacitor
of 100p between that resistor and the ground. If that's not enough you can
lower the resistor and raise the capacitor value until you achive the result
you want.

petrus bitbyter

On Wed, 21 Mar 2007 14:17:19 +1100, Kevin Brooks
wrote:

Below is linked the circuit as you have kindly suggested. I am still
not getting a 10.5Hz squarewave from pin 13. Have tried varying the RC
values to no avail.

The other outputs have irregular pulse widths at strange frequencies
as well, none of which correspond to the maths of adding the divisors.

http://home.iprimus.com.au/loungecinema/cd4040.gif

I garther from your previous comments this is an untidy design
approach. Is it, in fact, a lost cause? What is the best solution for
a progammable divide by N? I am trying to keep chip count down.

I saw another design that ran the reset through a 74HC74. Would that
help?

I know about the CD4059 but prefer not to go BCD.

---
I'd use an HC40103.

If you can stand an asymmetrical clock for your divided-down output
use TC directly. If you can't, divide by half of 195 and then use
TC as the clock input of a "D" type flip-flop wired as a divide by
two. in order to divide by 195/2 you'll need to divide by 98 for
one cycle and 97 for the next, toggling each time, but you can do
that with the other half of an HC74.

Would you like a schematic?


--
JF

On Wed, 21 Mar 2007 11:02:14 -0500, John Fields
wrote:


---
I'd use an HC40103.

If you can stand an asymmetrical clock for your divided-down output
use TC directly. If you can't, divide by half of 195 and then use
TC as the clock input of a "D" type flip-flop wired as a divide by
two. in order to divide by 195/2 you'll need to divide by 98 for
one cycle and 97 for the next, toggling each time, but you can do
that with the other half of an HC74.

Would you like a schematic?

---
Slow day today, it's attached. :-)


--
JF

Many thanks John. Wouldn't we love to see a book of building block
circuits like this. I'm really just an oldie waiting for analog to
come back.

Kevin Brooks



On Wed, 21 Mar 2007 13:27:23 -0500, John Fields
wrote:

On Wed, 21 Mar 2007 11:02:14 -0500, John Fields
wrote:


---
I'd use an HC40103.

If you can stand an asymmetrical clock for your divided-down output
use TC directly. If you can't, divide by half of 195 and then use
TC as the clock input of a "D" type flip-flop wired as a divide by
two. in order to divide by 195/2 you'll need to divide by 98 for
one cycle and 97 for the next, toggling each time, but you can do
that with the other half of an HC74.

Would you like a schematic?

---
Slow day today, it's attached. :-)