On Wed, 21 Mar 2007 14:17:19 +1100, Kevin Brooks
wrote:

Below is linked the circuit as you have kindly suggested. I am still
not getting a 10.5Hz squarewave from pin 13. Have tried varying the RC
values to no avail.

The other outputs have irregular pulse widths at strange frequencies
as well, none of which correspond to the maths of adding the divisors.

http://home.iprimus.com.au/loungecinema/cd4040.gif

I garther from your previous comments this is an untidy design
approach. Is it, in fact, a lost cause? What is the best solution for
a progammable divide by N? I am trying to keep chip count down.

I saw another design that ran the reset through a 74HC74. Would that
help?

I know about the CD4059 but prefer not to go BCD.

---
I'd use an HC40103.

If you can stand an asymmetrical clock for your divided-down output
use TC directly. If you can't, divide by half of 195 and then use
TC as the clock input of a "D" type flip-flop wired as a divide by
two. in order to divide by 195/2 you'll need to divide by 98 for
one cycle and 97 for the next, toggling each time, but you can do
that with the other half of an HC74.

Would you like a schematic?


--
JF