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Default Slightly misbehaving switcher (from SED discussion)

Hello Joerg,

[DSP DLL losing lock with small output caps...]

"Joerg" wrote in message
...
This is not good at all. Something on that DSP seems to be quite marginal if
a wee ripple can knock it off the rocker.


Yeah, I certainly agree. It deserves closer examination, although it wasn't
part of the overall circuit I was involved in and hence thus far I've just
been adding bigger caps when asked to do so. :-) I'll mention your comments
to the guy who did the DSP circuitry... we probably should at least stand over
the PCB and key up a 5W HT and see whether or not the board explodes...

---Joel


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Default Slightly misbehaving switcher (from SED discussion)

Joel Koltner wrote:
This is the first cut of the production department's layout for this switcher.
I saw "first cut" because IMO it needs some serious adjustment -- with the
most obvious problem being the distance between L3 and C87. This is an
8-layer board (don't ask), and both ground and the output of the switcher
("Vcore") go to their own dedicated planes whereas the switcher's input
("VBAT") is a larger copper pour on another layer. (I've turned off the
layers other than the top as none of the switcher's nets are routed on them
and they make for a considerably messier plot... C28 and C30 are decoupling
the power pins on a connector that's on the bottom side of the board, if
anyone's curious.)


I would move C86 right up against pin 4 and 6 (with the
trance under the chip to pins 4 and 6, and then put C87
right against C86.

--
Regards,

John Popelish
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Default Slightly misbehaving switcher (from SED discussion)

On Tue, 19 Feb 2008 11:09:43 -0800, "Joel Koltner"
wrote:

This is the first cut of the production department's layout for this switcher.
I saw "first cut" because IMO it needs some serious adjustment -- with the
most obvious problem being the distance between L3 and C87. This is an
8-layer board (don't ask), and both ground and the output of the switcher
("Vcore") go to their own dedicated planes whereas the switcher's input
("VBAT") is a larger copper pour on another layer. (I've turned off the
layers other than the top as none of the switcher's nets are routed on them
and they make for a considerably messier plot... C28 and C30 are decoupling
the power pins on a connector that's on the bottom side of the board, if
anyone's curious.)


8 layers, and none of them visible. What can you say? I don't get the
VBAT pour, unless it's a heatsink.

This is a simplified schematic - hope you're sure you don't need all
those old parts.

All those colour coded vias are cute. You should still avoid acute
copper details where they hit track (grey round artifact near R40?)

Legible designators that don't cover through-holes, or pads are nice.
Component art should avoid it, too.

I'd go for better thermal transfer on the ground pin, or Vin,
depending on chip construction, anyways. It's free.

RL
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Default Slightly misbehaving switcher (from SED discussion)

Hi RL,

"legg" wrote in message
...
8 layers, and none of them visible.


The top layer's visible and, other than the plane layers, that's the only one
used for routing anything on the schematic shown. (There's lots of other
stuff on that board, but I'm not at liberty to post it publically.)

What can you say? I don't get the
VBAT pour, unless it's a heatsink.


VBat powers several other regulators as well as carrying upwards of 3A while
the battery charges, so I suspect the layout guy figured it was easier to just
use a pour on part of a spare layer he had around than routing it everywhere.

This is a simplified schematic - hope you're sure you don't need all
those old parts.


Hmm?

All those colour coded vias are cute.


Yeah, that practice isn't something I'd seen before until I encountered PADS.
I rather like it now, although the guy who did this layout tends to color more
nets than I do.

You should still avoid acute
copper details where they hit track (grey round artifact near R40?)


Grey is actually both Vcore and the silkscreen... that dot near R40 is the pin
1 (silkscreen) indicator for the IC (U11).

Legible designators that don't cover through-holes, or pads are nice.
Component art should avoid it, too.


Agreed.

I'd go for better thermal transfer on the ground pin, or Vin,
depending on chip construction, anyways. It's free.


Thanks, I'll make a note of that.

---Joel


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Default Slightly misbehaving switcher (from SED discussion)

On Tue, 19 Feb 2008 11:09:43 -0800, "Joel Koltner"
wrote:

This is the first cut of the production department's layout for this switcher.
I saw "first cut" because IMO it needs some serious adjustment -- with the
most obvious problem being the distance between L3 and C87. This is an
8-layer board (don't ask), and both ground and the output of the switcher
("Vcore") go to their own dedicated planes whereas the switcher's input
("VBAT") is a larger copper pour on another layer. (I've turned off the
layers other than the top as none of the switcher's nets are routed on them
and they make for a considerably messier plot... C28 and C30 are decoupling
the power pins on a connector that's on the bottom side of the board, if
anyone's curious.)

Critiques are always welcome!

---Joel

Boy, this breaks all the rules for switcher layout! Normally, you have
copper pours on the same surface as your controller IC to the various
high-current handling parts (C86, C87, L3, U11). Vias connecting the
nasty parts to a general plane are a really bad idea. Poor pin-4 may
be very unhappy with C86 and R29 connected the way they are. One of my
colleagues did this sort of layout and had a really hard time getting
the switcher to behave. A wire jumper between two ground plane
connected component terminals cleared up the issues (probably the
equivalent of U11-4 and the ground terminal of C86).

---
Mark


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Default Slightly misbehaving switcher (from SED discussion)

Hi Mark,

"qrk" wrote in message
...
Boy, this breaks all the rules for switcher layout!


Yeah, it does...

Thanks for the comments; this will be an interesting experiment in how far you
can bend the rules but still have plane layers come to your rescue, I guess.
:-)

---Joel


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