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legg legg is offline
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Default Slightly misbehaving switcher (from SED discussion)

On Tue, 19 Feb 2008 11:09:43 -0800, "Joel Koltner"
wrote:

This is the first cut of the production department's layout for this switcher.
I saw "first cut" because IMO it needs some serious adjustment -- with the
most obvious problem being the distance between L3 and C87. This is an
8-layer board (don't ask), and both ground and the output of the switcher
("Vcore") go to their own dedicated planes whereas the switcher's input
("VBAT") is a larger copper pour on another layer. (I've turned off the
layers other than the top as none of the switcher's nets are routed on them
and they make for a considerably messier plot... C28 and C30 are decoupling
the power pins on a connector that's on the bottom side of the board, if
anyone's curious.)


8 layers, and none of them visible. What can you say? I don't get the
VBAT pour, unless it's a heatsink.

This is a simplified schematic - hope you're sure you don't need all
those old parts.

All those colour coded vias are cute. You should still avoid acute
copper details where they hit track (grey round artifact near R40?)

Legible designators that don't cover through-holes, or pads are nice.
Component art should avoid it, too.

I'd go for better thermal transfer on the ground pin, or Vin,
depending on chip construction, anyways. It's free.

RL