Hi RL,

"legg" wrote in message
...
8 layers, and none of them visible.

The top layer's visible and, other than the plane layers, that's the only one
used for routing anything on the schematic shown. (There's lots of other
stuff on that board, but I'm not at liberty to post it publically.)

What can you say? I don't get the
VBAT pour, unless it's a heatsink.

VBat powers several other regulators as well as carrying upwards of 3A while
the battery charges, so I suspect the layout guy figured it was easier to just
use a pour on part of a spare layer he had around than routing it everywhere.

This is a simplified schematic - hope you're sure you don't need all
those old parts.

Hmm?

All those colour coded vias are cute.

Yeah, that practice isn't something I'd seen before until I encountered PADS.
I rather like it now, although the guy who did this layout tends to color more
nets than I do.

You should still avoid acute
copper details where they hit track (grey round artifact near R40?)

Grey is actually both Vcore and the silkscreen... that dot near R40 is the pin
1 (silkscreen) indicator for the IC (U11).

Legible designators that don't cover through-holes, or pads are nice.
Component art should avoid it, too.

Agreed.

I'd go for better thermal transfer on the ground pin, or Vin,
depending on chip construction, anyways. It's free.

Thanks, I'll make a note of that.

---Joel