I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg

And re-drew it as follows.

http://members.ozemail.com.au/~bisagoma/step_gen.jpg

But ... it does not appear to work as described. The input is a 512 Hz
clock pulse. The output on pin 3 of the CD4051 is a slightly noisey
plain squarewave divided by 32 (16Hz). IOW no steps.

Can anyone point out a design fault in this circuit or other reason
why it might not work?

Lewis

Lewis Carson a écrit :
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg

And re-drew it as follows.

http://members.ozemail.com.au/~bisagoma/step_gen.jpg

But ... it does not appear to work as described. The input is a 512 Hz
clock pulse. The output on pin 3 of the CD4051 is a slightly noisey
plain squarewave divided by 32 (16Hz). IOW no steps.

Can anyone point out a design fault in this circuit or other reason
why it might not work?


Sure. You need the opamp stage at the 4051 output.
A small cap (1n or so) across the 1K feedback resistor will be welcomed too.

--
Thanks,
Fred.

"Fred Bartoli" r_AndThisToo
wrote in message ...
A small cap (1n or so) across the 1K feedback resistor will be welcomed too.

Is that meant to surpress any spikes when the '4051 switches (i.e,. if it
"breaks" before it "makes")?

It's kind of a clever circuit, IMO. What do the circuit design gurus think of
it?

I'm waiting to hear someone suggest you could do this with an 8 pin PIC or
AVR... 4 lines to the '4051, and another one to receive frequency commands
over, e.g., RS-232. :-)

"Lewis Carson" wrote in message
...
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg

And re-drew it as follows.

http://members.ozemail.com.au/~bisagoma/step_gen.jpg

But ... it does not appear to work as described. The input is a 512 Hz
clock pulse. The output on pin 3 of the CD4051 is a slightly noisey
plain squarewave divided by 32 (16Hz). IOW no steps.

Can anyone point out a design fault in this circuit or other reason
why it might not work?

Lewis

And pin 7 of the 4051 need to go to 0V



--
Posted via a free Usenet account from http://www.teranews.com

On Fri, 30 Mar 2007 16:05:14 -0700, "Joel Kolstad"
wrote:

"Fred Bartoli" r_AndThisToo
wrote in message ...
A small cap (1n or so) across the 1K feedback resistor will be welcomed too.

Is that meant to surpress any spikes when the '4051 switches (i.e,. if it
"breaks" before it "makes")?

It's kind of a clever circuit, IMO. What do the circuit design gurus think of
it?

I'm waiting to hear someone suggest you could do this with an 8 pin PIC or
AVR... 4 lines to the '4051, and another one to receive frequency commands
over, e.g., RS-232. :-)


Just connect four pic pins to an output node with 1k, 2k, 4k, and 8k
resistors, and you're done.

John

"John Larkin" wrote in message
...
On Fri, 30 Mar 2007 16:05:14 -0700, "Joel Kolstad"
wrote:

"Fred Bartoli"
r_AndThisToo
wrote in message ...
A small cap (1n or so) across the 1K feedback resistor will be welcomed
too.

Is that meant to surpress any spikes when the '4051 switches (i.e,. if it
"breaks" before it "makes")?

It's kind of a clever circuit, IMO. What do the circuit design gurus
think of
it?

I'm waiting to hear someone suggest you could do this with an 8 pin PIC
or
AVR... 4 lines to the '4051, and another one to receive frequency
commands
over, e.g., RS-232. :-)


Just connect four pic pins to an output node with 1k, 2k, 4k, and 8k
resistors, and you're done.

John


Seems about 30% THD?.



--
Posted via a free Usenet account from http://www.teranews.com

On Sat, 31 Mar 2007 02:18:09 +0100, "john jardine"
wrote:


"John Larkin" wrote in message
.. .
On Fri, 30 Mar 2007 16:05:14 -0700, "Joel Kolstad"
wrote:

"Fred Bartoli"
fred._canxxxel_this_bartoli@RemoveThatAlso_free. fr_AndThisToo
wrote in message ...
A small cap (1n or so) across the 1K feedback resistor will be welcomed
too.

Is that meant to surpress any spikes when the '4051 switches (i.e,. if it
"breaks" before it "makes")?

It's kind of a clever circuit, IMO. What do the circuit design gurus
think of
it?

I'm waiting to hear someone suggest you could do this with an 8 pin PIC
or
AVR... 4 lines to the '4051, and another one to receive frequency
commands
over, e.g., RS-232. :-)


Just connect four pic pins to an output node with 1k, 2k, 4k, and 8k
resistors, and you're done.

John


Seems about 30% THD?.

Is that what you get with 16 amplitude levels spaced, presumably, at
16 even time intervals? I'd guess somewhat better than 30%; a square
wave is only 43. Possibly you could make a better sine wave if the
resistors weren't binary weighted. More math than I care to sign up
for!

We just did a homebrew 8-channel DDS waveform generator, with 16-bit
math and 14-bit dacs, 2048 point sine lookup table. Sinewaves look
pretty good.

John

"John Larkin" wrote in message
...
[...]
Seems about 30% THD?.

Is that what you get with 16 amplitude levels spaced, presumably, at
16 even time intervals? I'd guess somewhat better than 30%; a square
wave is only 43. Possibly you could make a better sine wave if the
resistors weren't binary weighted. More math than I care to sign up
for!

I'd envisioned a clean triangle. (3rd harmonic at 1/3rd of primary).

We just did a homebrew 8-channel DDS waveform generator, with 16-bit
math and 14-bit dacs, 2048 point sine lookup table. Sinewaves look
pretty good.

John


Nice!.
Sounds like you've been disenchanted with the performance of the AD chips.



--
Posted via a free Usenet account from http://www.teranews.com

Thank you all for the responses. But to clarify my original question,
is there anything wrong with the circuit below or not? Is the design
flawed or incorrectly implemented?

Thanks,

Lewis


On Sat, 31 Mar 2007 07:30:53 +1000, Lewis Carson
wrote:

I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg

And re-drew it as follows.

http://members.ozemail.com.au/~bisagoma/step_gen.jpg

But ... it does not appear to work as described. The input is a 512 Hz
clock pulse. The output on pin 3 of the CD4051 is a slightly noisey
plain squarewave divided by 32 (16Hz). IOW no steps.

Can anyone point out a design fault in this circuit or other reason
why it might not work?

Lewis

"Lewis Carson" wrote in message
...
Thank you all for the responses. But to clarify my original question,
is there anything wrong with the circuit below or not? Is the design
flawed or incorrectly implemented?

Thanks,

Lewis


On Sat, 31 Mar 2007 07:30:53 +1000, Lewis Carson
wrote:

I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg
I found this circuit online.

http://members.ozemail.com.au/~bisagoma/step_sine.jpg

And re-drew it as follows.

http://members.ozemail.com.au/~bisagoma/step_gen.jpg

But ... it does not appear to work as described. The input is a 512 Hz
clock pulse. The output on pin 3 of the CD4051 is a slightly noisey
plain squarewave divided by 32 (16Hz). IOW no steps.

Can anyone point out a design fault in this circuit or other reason
why it might not work?

Lewis


Someone already told you how to fix your drawing. You need to put the opamp, or
at least a load resistance, on the output of the mux. Otherwise, the resistor
chain is open-ended, no current is being passed through them, therefore, you're
seeing only the sum of the 4040 outputs, which are all CMOS level square waves.
Remember, the 4040 is an analog switch. It only makes a path from input to
output, it doesn't source or sink anything at the output except what is applied
to the inputs.

--
Dave M
MasonDG44 at comcast dot net (Just substitute the appropriate characters in the
address)

Life is like a roll of toilet paper; the closer to the end, the faster it goes.

On Sat, 31 Mar 2007 15:39:19 +0100, "john jardine"
wrote:


"John Larkin" wrote in message
.. .
[...]
Seems about 30% THD?.

Is that what you get with 16 amplitude levels spaced, presumably, at
16 even time intervals? I'd guess somewhat better than 30%; a square
wave is only 43. Possibly you could make a better sine wave if the
resistors weren't binary weighted. More math than I care to sign up
for!

I'd envisioned a clean triangle. (3rd harmonic at 1/3rd of primary).

We just did a homebrew 8-channel DDS waveform generator, with 16-bit
math and 14-bit dacs, 2048 point sine lookup table. Sinewaves look
pretty good.

John


Nice!.
Sounds like you've been disenchanted with the performance of the AD chips.

We wanted the flexibility to do other/arbitrary waveforms, pulses,
modulation, and channel-channel phase shifts on later versions. And to
program amplitude. And it was fun to roll our own DDS.

John