"Henry" apl2research(.a.t.)comcast.net wrote in message
. ..
Hey guys. Thanks for the reply.

petrus bitbyter: I did compare the waveforms of the datasheets and they
do match up, or I should say they match to my eye. The board I'm
working with is actually an expansion board to another card. I guess
I'll have to draw the schematic to the main card to really understand
how and what the main card is doing and what it expects from the
daughter board. Thanks for the advice!


Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the
right place on the data sheets I see the 1bit DRAM requires 512 cycles
every 8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't
this the same thing or am I confusing something? Thanks.
The problem is that two lots of 512 cycles, do not activate the extra
address line, that a '1024' cycle refresh implies...

Best Wishes

Hello Roger.

I'm not sure I understand what you mean about 'The problem is that two lots
of 512 cycles, do not activate the extra address line, that a '1024' cycle
refresh implies...'.

Well, from what I believe is going on my card is set to refresh 512 address
lines every 8 milliseconds - or at least that is what the data sheet for the
1bit DRAM says it needs. Since the 1bit DRAM's work I will assume those are
the numbers then. The DRAM I believe has a built in counter to advance the
CAS address lines automatically from the LAST line it had accessed in
refresh mode - so you don't need to apply all the possible address to the
DRAM and eat up CPU time. Now if the DRAM is just idle and not being
accessed then the current scheme will work just fine - i.e. - 512 refreshes
in 8ms, 2 cycles of 512 = 1024 in 16ms. So that's good, or so I would
think.

Now what happens when the DRAM is at line 0 and the refresh kicks in? Of
course it receive 512 cycles and the counter will now be on line 511. Now I
access the DRAM in between the first 512 refresh and the second refresh and
read or write data to line 0. The refresh then kicks in again after my read
or write and advances the counter from the LAST line I accessed which was 0,
to 511, thus missing the other 512 lines that still need to be refreshed.
Now what if I access line 0 again just after that refresh and then the
refresh kicks in again?

I think this is what both of you have been talking about. Where if the
board was designed to refresh 1024 times per refresh cycle then it's
guarantied that every line of the array would be refreshed no matter what
line in the array was last accessed. Am I following correctly?

On another side test I tried a RAM board that used 256k x 1bit DRAM's. I
replaced 4 of them with a 256k x 4bit DRAM. Same type of issue as with the
1Meg DRAM's. Also the same refresh numbers issue as the 1 Meg DRAM's - that
the 4bit DRAM refresh cycles are double that of the 1bit DRAM. It's the
only thing that I can see is really that different between the two
datasheets. In every case that I can see the 4bit DRAM specs are well
within operating in a 1bit design - all but the refresh cycle numbers. As
for the technical stuff, the 2 timing values that are relevant, that I see,
are tCSR and tCHR. On the 1Mx1 chips, their min values are 10 and 15,
respectively. With the 1Mx4 chips, I see 5 and 15. Looks to me that the
1Mx4 chips are just as compatible (note: there's no value listed as in the
max column for either chip). Even the tRPC value, which I'm not sure is a
factor, is a min of 10 on the x1 and a 0 on the x4. The only real
difference seems to be the refresh cycles which I now assume correspond
directly to the memory array in the DRAM IC.

I also believe my board to be doing /CAS-before-/RAS refresh but I can't say
for sure. Any good 'test' to see if my assumption is correct? Wish I had a
scope.

Any clarification to any of my thoughts/statements is always appreciated.


Henry


"Roger Hamlett" wrote in message
...

"Henry" apl2research(.a.t.)comcast.net wrote in message
. ..
Hey guys. Thanks for the reply.

petrus bitbyter: I did compare the waveforms of the datasheets and they
do match up, or I should say they match to my eye. The board I'm working
with is actually an expansion board to another card. I guess I'll have
to draw the schematic to the main card to really understand how and what
the main card is doing and what it expects from the daughter board.
Thanks for the advice!


Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the
right place on the data sheets I see the 1bit DRAM requires 512 cycles
every 8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't
this the same thing or am I confusing something? Thanks.
The problem is that two lots of 512 cycles, do not activate the extra
address line, that a '1024' cycle refresh implies...

Best Wishes

Well, I see I'm still not on the right track.

I buddy of mine just sent me a .PDF about DRAM refresh. Here it is:
http://reactivecomputers.gotdns.com/...%20Refresh.pdf

I'm under the assumption that my board uses CAS Before RAS refresh. After
reading the data sheet I'm now guessing it doesn't. Now to buy a scope! ;-)

Also after reading the data sheet I now have no idea what either Helmut or
petrus bitbyter were trying to tell me when the mentioned the 1024 cycles
issue. According to the data sheet IF my board is using CAS Before RAS
refresh (or CBR) then as long as a refresh is done every 15.6us then I
should be able to use ANY DRAM with the same requirements.

So I'm basically as lost as I was before. :-( I think?


Henry


"Henry" apl2research(.a.t.)comcast.net wrote in message
...
Hello Roger.

I'm not sure I understand what you mean about 'The problem is that two
lots of 512 cycles, do not activate the extra address line, that a '1024'
cycle refresh implies...'.

Well, from what I believe is going on my card is set to refresh 512
address lines every 8 milliseconds - or at least that is what the data
sheet for the 1bit DRAM says it needs. Since the 1bit DRAM's work I will
assume those are the numbers then. The DRAM I believe has a built in
counter to advance the CAS address lines automatically from the LAST line
it had accessed in refresh mode - so you don't need to apply all the
possible address to the DRAM and eat up CPU time. Now if the DRAM is just
idle and not being accessed then the current scheme will work just fine -
i.e. - 512 refreshes in 8ms, 2 cycles of 512 = 1024 in 16ms. So that's
good, or so I would think.

Now what happens when the DRAM is at line 0 and the refresh kicks in? Of
course it receive 512 cycles and the counter will now be on line 511. Now
I access the DRAM in between the first 512 refresh and the second refresh
and read or write data to line 0. The refresh then kicks in again after
my read or write and advances the counter from the LAST line I accessed
which was 0, to 511, thus missing the other 512 lines that still need to
be refreshed. Now what if I access line 0 again just after that refresh
and then the refresh kicks in again?

I think this is what both of you have been talking about. Where if the
board was designed to refresh 1024 times per refresh cycle then it's
guarantied that every line of the array would be refreshed no matter what
line in the array was last accessed. Am I following correctly?

On another side test I tried a RAM board that used 256k x 1bit DRAM's. I
replaced 4 of them with a 256k x 4bit DRAM. Same type of issue as with
the 1Meg DRAM's. Also the same refresh numbers issue as the 1 Meg
DRAM's - that the 4bit DRAM refresh cycles are double that of the 1bit
DRAM. It's the only thing that I can see is really that different between
the two datasheets. In every case that I can see the 4bit DRAM specs are
well within operating in a 1bit design - all but the refresh cycle
numbers. As for the technical stuff, the 2 timing values that are
relevant, that I see, are tCSR and tCHR. On the 1Mx1 chips, their min
values are 10 and 15, respectively. With the 1Mx4 chips, I see 5 and 15.
Looks to me that the 1Mx4 chips are just as compatible (note: there's no
value listed as in the max column for either chip). Even the tRPC value,
which I'm not sure is a factor, is a min of 10 on the x1 and a 0 on the
x4. The only real difference seems to be the refresh cycles which I now
assume correspond directly to the memory array in the DRAM IC.

I also believe my board to be doing /CAS-before-/RAS refresh but I can't
say for sure. Any good 'test' to see if my assumption is correct? Wish I
had a scope.

Any clarification to any of my thoughts/statements is always appreciated.


Henry


"Roger Hamlett" wrote in message
...

"Henry" apl2research(.a.t.)comcast.net wrote in message
. ..
Hey guys. Thanks for the reply.

petrus bitbyter: I did compare the waveforms of the datasheets and they
do match up, or I should say they match to my eye. The board I'm
working with is actually an expansion board to another card. I guess
I'll have to draw the schematic to the main card to really understand
how and what the main card is doing and what it expects from the
daughter board. Thanks for the advice!


Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the
right place on the data sheets I see the 1bit DRAM requires 512 cycles
every 8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't
this the same thing or am I confusing something? Thanks.
The problem is that two lots of 512 cycles, do not activate the extra
address line, that a '1024' cycle refresh implies...

Best Wishes

"Henry" apl2research(.a.t.)comcast.net wrote in message
. ..

Hi Henry,

Good on you for keeping the side up, I too have enjoyed doing some of these
things with some of the 80's computers.

Type in "atari st 72-pin upgrade" into Google. Might help 1% maybe :-)
Mine is the only 72-pin hack out there for the ST :-) I muddled through
most of it so may not be as detailed in terms of RAS cycles and alike here.

Hope to see you write up your experiences in the future.

Best of luck,

Alison