An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" wrote in
message ...
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

View in fixed-pitch:

__
A ---o-------------| \
| | )o-.
| .--|__/ |
| | |
| __ | | __
'--| \ | '--| \
| )o--o | )o---A xor B
.--|__/ | .--|__/
| | |
| | __ |
| '--| \ |
| | )o-'
B ---o-------------|__/

On Mon, 7 Mar 2011 19:46:36 -0000, "Andrew Holme"
wrote:


"Jim Thompson" wrote in
message ...
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

View in fixed-pitch:

__
A ---o-------------| \
| | )o-.
| .--|__/ |
| | |
| __ | | __
'--| \ | '--| \
| )o--o | )o---A xor B
.--|__/ | .--|__/
| | |
| | __ |
| '--| \ |
| | )o-'
B ---o-------------|__/




I didn't explain well enough...

When B is low, A propagates to the output non-inverted... 2 stage
delay

When B is high A propagates to the output inverted... 3 stage delay

I'm looking for some scheme where both paths are equal delay.

I can see how to do it in PECL (which is really analog :-), but not in
CMOS :-(

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

On 03/07/2011 11:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

I vaguely remember seeing a picture of this done at the transistor
level, in CMOS, with a structure reminiscent of a trimmed-down Gilbert
cell mixer.

But I'm not sure if I could give the actual circuit if my life depended
on it.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

On Mon, 07 Mar 2011 13:59:44 -0800, Tim Wescott
wrote:

On 03/07/2011 11:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

I vaguely remember seeing a picture of this done at the transistor
level, in CMOS, with a structure reminiscent of a trimmed-down Gilbert
cell mixer.

But I'm not sure if I could give the actual circuit if my life depended
on it.

At least in the 1970's ECL 10000 gate the basic logical element was
the OR/NOR gate consisting of an differential amplifier followed by
emitter followers.

The ECL 10K Excusive-OR gate was implemented by a cascaded Gilbert
differential stage followed by level shifters,

On Tue, 08 Mar 2011 02:14:16 +0200, wrote:

On Mon, 07 Mar 2011 13:59:44 -0800, Tim Wescott
wrote:

On 03/07/2011 11:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

I vaguely remember seeing a picture of this done at the transistor
level, in CMOS, with a structure reminiscent of a trimmed-down Gilbert
cell mixer.

But I'm not sure if I could give the actual circuit if my life depended
on it.

At least in the 1970's ECL 10000 gate the basic logical element was
the OR/NOR gate consisting of an differential amplifier followed by
emitter followers.

The ECL 10K Excusive-OR gate was implemented by a cascaded Gilbert
differential stage followed by level shifters,

Yes, but it wasn't called a Gilbert cell yet ;-)

(In the very early '60's, I was at Motorola, where ECL was first
developed... Jan Narud was my first non-academic boss.)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

On 8/03/2011 5:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

A small look-up table?

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On 11-03-07 12:20 PM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson


The truth tables here may be of help:

http://www.kpsec.freeuk.com/gates.htm#summary



mike


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"Jim Thompson" wrote in message
...

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
-------------------

I am not sure where you get the uneven propagation delays.
Perhaps you are considering both logic levels switching at one time? I would
assume the logic inversion control input would already be quiescent.

(thinking out loud here)
Exclusive OR gates are quite simple complex gates (confusion intended)


Simply English text stated A or B but not both.

This equates to three simple gates

an OR gate = A+B 'this is the OR part, obviously
an NAND gate = NOT(A*B) 'this is the not both part
and one to combine the logic on the output 'this is what combines the two
conditions
AND = (A+B) * (NOT(A*B)

Now when A input is true (overall inversion) the A+B gate becomes blocked
at the output AND gate when B goes true.
Yup, the active NAND input gate NOT(A*B) has an extra inversion stage to
control the O/P AND gate.

When A input is false (no overall inversion) the A+B gate predominates at
the output of the AND gate when B goes true.
The inactive NAND input gate NOT(A*B) is not functioning in the output
signal through the O/P AND gate.

The same number of simple gates are used each logic but the transistor
stages are the same.

Perhaps slip a simple buffer into the output of the input OR gate to
increase it's propagation. Now you would have to find one with the same
number of stages as the NAND has for inversion hmmmm... not likely.

What type of logic family are you attempting to do this with? Logic insides
need to be known for this one.

Spec sheets are needed to spec propagation delay.


mike

"Jim Thompson" wrote in message
...

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
---------------------------

One other comment here.

This whole thing may be BS as NAND gates were a more natural logic using
transistors as they took less transistors to create. NAND and NOR gates can
be accomplished with one stage or transistors.

AND and simple OR gates had an extra inversion stage to make them operate
with their logic and thus had more propagation delay.

Been a long time since I studied the inside circuitry of logic gate
families. My boss insisted we knew everything about an IC before tackling
any repairs. Of course we usually fixed the problem when he went to answer
the phone. Got years of chasing electrons experience, though.


mike

"Jim Thompson" wrote in
message ...
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

Hello:

Have you tried transmission gates?
See:
http://tams-www.informatik.uni-hambu...xor-tgate.html
You need java to view it (sorry for that)

Best Regards

Steve Sousa

On Mon, 07 Mar 2011 12:20:13 -0700, Jim Thompson wrote:

An XOR is a convenient structure to allow a control signal to invert or
non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

Never rolled my own at the device level but can you drive A through a
tristate inverter and a tristate buffer and then use B to select the
output?



--
Joe Chisolm
Marble Falls, Tx.

On Tue, 08 Mar 2011 11:22:52 -0600, Joe Chisolm
wrote:

On Mon, 07 Mar 2011 12:20:13 -0700, Jim Thompson wrote:

An XOR is a convenient structure to allow a control signal to invert or
non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

Never rolled my own at the device level but can you drive A through a
tristate inverter and a tristate buffer and then use B to select the
output?

I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Jim Thompson wrote:

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

Do the delays have to be symmetrical? In other words, if we give you an A
XOR B where A is the signal and has 3 stage delays regardless of B state,
will B ever be used as the signal (requiring 3 stage delays for either A
state?

--
Paul Hovnanian
------------------------------------------------------------------
A mathematician is a machine for converting coffee into theorems.

"Tim Wescott" wrote .
On 03/07/2011 11:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

I vaguely remember seeing a picture of this done at the transistor level,
in CMOS, with a structure reminiscent of a trimmed-down Gilbert cell
mixer.
But I'm not sure if I could give the actual circuit if my life depended on
it.


I do remember it. I saw it inside a TTL EXOR circuit, maybe the 7486.
Two NPN's, E and B cross connected to open collector drivers (A and B),
output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2


Regards,
Arie de Muynck

On Tue, 08 Mar 2011 10:30:56 -0700, Jim Thompson wrote:

On Tue, 08 Mar 2011 11:22:52 -0600, Joe Chisolm
wrote:

On Mon, 07 Mar 2011 12:20:13 -0700, Jim Thompson wrote:

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

Never rolled my own at the device level but can you drive A through a
tristate inverter and a tristate buffer and then use B to select the
output?

I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.

...Jim Thompson

Since you are rolling your own start with a 7474 D flop with /pre
and /clr. That would give you your Q and /Q. Strip out the clk gates
and just drive the /pre and /clr. The old data sheet for the SN7474
is still on the TI web site with the TTL schematic. The newer parts
like the 74ahc74 have logic diagrams. What is your A-out timing budget?




--
Joe Chisolm
Marble Falls, Tx.

"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the 7486.
Two NPN's, E and B cross connected to open collector drivers (A and B),
output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2


And of course it needed some pull-ups on the O.C. drivers as well...

pull-up
|
A --+-- E1 -- B2 pull-up
|
pull-up C1 -- C2 --+--- OUT
|
B --+-- B1 -- E2


Arie

On 03/08/2011 11:30 AM, Jim Thompson wrote:


I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.
Oh, much better would be to make a differential driver circuit. I'd
suggest some relevant chips, but I think you said you were building it
from primitives.

Jon

On Tue, 08 Mar 2011 17:27:41 -0600, Jon Elson
wrote:

On 03/08/2011 11:30 AM, Jim Thompson wrote:


I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.
Oh, much better would be to make a differential driver circuit. I'd
suggest some relevant chips, but I think you said you were building it
from primitives.

Jon

I'm doing a high-speed 3.3V to 5V translator, where "5V" may be just
about anywhere 3V to 5.5V ;-)

But I think I've figured out a way to avoid the funny "lumpy" risetime
I'm seeing. Looks like, rather than perfect delay match, sequencing
delay mismatch depending on transition direction may smooth it out.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Jim Thompson wrote:


An XOR is a convenient structure to allow a control signal to invert or
non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.

How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

That is a simple OR gate. He wants an XOR gate.

-----------------
"Vladimir Vassilevsky" wrote in message
...
How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?




m II wrote:
That is a simple OR gate. He wants an XOR gate.

-----------------
"Vladimir Vassilevsky" wrote in message
...
How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
Crazy idea..
NPN transistor with emitter to resistor to control signal, collector
with pullup resistor to +5; signal out at collector. Resistors of
similar value.

"Jim Thompson" schreef
in bericht ...
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

I think it's an analog problem rather then a logic one as logic does not
dive below gate level

A quick look makes me think the problem is caused by the input signals that
are to be inverted (3 stage) or not (2 stage). The old TTL chips provided
"complementary output elements", the SN74265. Using this elements instead of
normal inverters will provide 3 stage delays all the time.

petrus bitbyter

[top posting corrected for this thread format]

"Vladimir Vassilevsky" wrote in message
...

m II wrote:
That is a simple OR gate. He wants an XOR gate.

-----------------
"Vladimir Vassilevsky" wrote in message
...
How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?

----

It is obvious you do not understand the definition of an exclusive OR gate /
circuit.
All two input gates / circuits have four states of input. This is not
related to the internal circuitry of the gate / circuit.

Here is a truth table and explanation for you.
http://en.wikipedia.org/wiki/XOR_gate

Please try not embarrass your name, further, with your immature attacks.


mike

On 8/03/2011 11:08 AM, David Eather wrote:
On 8/03/2011 5:20 AM, Jim Thompson wrote:
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

A small look-up table?

I mean something like what is done with a PAL

On Tue, 08 Mar 2011 22:57:47 -0600, Vladimir Vassilevsky
wrote:


Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?




m II wrote:
That is a simple OR gate. He wants an XOR gate.

-----------------
"Vladimir Vassilevsky" wrote in message
...
How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

On Tue, 08 Mar 2011 16:49:07 -0700, Jim Thompson
wrote:

On Tue, 08 Mar 2011 17:27:41 -0600, Jon Elson
wrote:

On 03/08/2011 11:30 AM, Jim Thompson wrote:


I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.
Oh, much better would be to make a differential driver circuit. I'd
suggest some relevant chips, but I think you said you were building it
from primitives.

Jon

I'm doing a high-speed 3.3V to 5V translator, where "5V" may be just
about anywhere 3V to 5.5V ;-)

But I think I've figured out a way to avoid the funny "lumpy" risetime
I'm seeing. Looks like, rather than perfect delay match, sequencing
delay mismatch depending on transition direction may smooth it out.

...Jim Thompson
---
Time shim in one direction but not the other?

---
JF

On Wed, 09 Mar 2011 18:58:02 -0600, John Fields
wrote:

On Tue, 08 Mar 2011 16:49:07 -0700, Jim Thompson
wrote:

On Tue, 08 Mar 2011 17:27:41 -0600, Jon Elson
wrote:

On 03/08/2011 11:30 AM, Jim Thompson wrote:


I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.
Oh, much better would be to make a differential driver circuit. I'd
suggest some relevant chips, but I think you said you were building it
from primitives.

Jon

I'm doing a high-speed 3.3V to 5V translator, where "5V" may be just
about anywhere 3V to 5.5V ;-)

But I think I've figured out a way to avoid the funny "lumpy" risetime
I'm seeing. Looks like, rather than perfect delay match, sequencing
delay mismatch depending on transition direction may smooth it out.

...Jim Thompson
---
Time shim in one direction but not the other?

---
JF

A supposedly "symmetrical" structure with transition direction
peculiarities. Because of the VDD1/VDD2 "spec" I have to tip-toe
around cautiously ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Jim Thompson wrote:



Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-)

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1




On 11-03-10 08:00 AM, Vladimir Vassilevsky wrote:


Jim Thompson wrote:



Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-)

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com


So, how do the mosfets know there is only one input on? How do the
mosfets turn off when there are two inputs? Most mosfets are pretty
sensitive to the slightest gate voltage, so even one input would
probably turn both on at full blast. What you have there is an OR gate

What limits the base current on the output pnp transistor?

Also, shouldn't there be drain resistors to ground on those gates? I had
a mosfet turn on once by just static from my hand touching the
unresistored gate. I then put a 100k ohm drain resistor on it and the
problem went away.


mike (the REAL one)




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On Thu, 10 Mar 2011 09:00:01 -0600, Vladimir Vassilevsky
wrote:



Jim Thompson wrote:



Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-)

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

I'm not getting across to you. Describe how that works.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Jim Thompson wrote:

On Thu, 10 Mar 2011 09:00:01 -0600, Vladimir Vassilevsky
wrote:

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

http://www.abvolt.com/misc/xor.jpg

I'm not getting across to you. Describe how that works.

If the inputs are 01 or 10, both FETs are on, so the output = 1.
If the inputs are 00 or 11, only one of FETs is on, output = 0.
Minor technicalities omitted for clarity.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

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On 11-03-10 09:15 AM, Vladimir Vassilevsky wrote:

http://www.abvolt.com/misc/xor.jpg

I'm not getting across to you. Describe how that works.

If the inputs are 01 or 10, both FETs are on, so the output = 1.
If the inputs are 00 or 11, only one of FETs is on, output = 0.
Minor technicalities omitted for clarity.


I see only one input with two possible supplies.

mike (the REAL one)
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On Thu, 10 Mar 2011 10:15:49 -0600, Vladimir Vassilevsky
wrote:



Jim Thompson wrote:

On Thu, 10 Mar 2011 09:00:01 -0600, Vladimir Vassilevsky
wrote:

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

http://www.abvolt.com/misc/xor.jpg

I'm not getting across to you. Describe how that works.

If the inputs are 01 or 10, both FETs are on, so the output = 1.
If the inputs are 00 or 11, only one of FETs is on, output = 0.
Minor technicalities omitted for clarity.

Indeed ;-)

With the addition of ~10 additional components/gates I accomplish a
3-state machine (with only one input).

High: State 1

Float: State 2

Low: State 3


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity generator
(don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.


And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't it
be driven high and low? (IANAEE)


--

Reply in group, but if emailing add one more
zero, and remove the last word.

"Tom Del Rosso" wrote in message
...

Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity
generator (don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.

Maybe he just did not read this part of the thread. Or I'm blacklisted.
The beautiful symmetry should appeal to him.

And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't
it be driven high and low? (IANAEE)

No, hard driving one input high, the other low would overdrive conducting
B-E junctions.
And you need to pull the E's low hard to get the output at a logic low
level.
The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x
NPN):

|\ VCC
A --| -+------- E C -----+ |
|/ | B | (R)
\ /--(R)--+ | |
X +------+--- OUT
/ \--(R)--+ |
|\ | B |
B --| -+------- E C -----+
|/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie

On Thu, 10 Mar 2011 22:32:55 +0100, "Arie de Muynck"
wrote:


"Tom Del Rosso" wrote in message
m...

Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity
generator (don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.

Maybe he just did not read this part of the thread. Or I'm blacklisted.
The beautiful symmetry should appeal to him.

And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't
it be driven high and low? (IANAEE)

No, hard driving one input high, the other low would overdrive conducting
B-E junctions.
And you need to pull the E's low hard to get the output at a logic low
level.
The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x
NPN):

|\ VCC
A --| -+------- E C -----+ |
|/ | B | (R)
\ /--(R)--+ | |
X +------+--- OUT
/ \--(R)--+ |
|\ | B |
B --| -+------- E C -----+
|/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie

You missed the part where what I really need is two circuits, each
with input A, but one with output A and the other with output Abar,
delay to each output EQUAL.

What is your preference in dry white wine ?:-)

Unfortunately I'm on the wagon at the moment. Something untoward
going on in my colon. Colonoscopy scheduled for Tuesday. Damned
capitalist health care... 1 week delay (from Doctor's order) while I'm
weaned from anti-inflammatory which could cause bleeding ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

Jim Thompson wrote:

On Thu, 10 Mar 2011 22:32:55 +0100, "Arie de Muynck"
wrote:


"Tom Del Rosso" wrote in message
m...

Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity
generator (don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.

Maybe he just did not read this part of the thread. Or I'm blacklisted.
The beautiful symmetry should appeal to him.

And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't
it be driven high and low? (IANAEE)

No, hard driving one input high, the other low would overdrive conducting
B-E junctions.
And you need to pull the E's low hard to get the output at a logic low
level.
The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x
NPN):

|\ VCC
A --| -+------- E C -----+ |
|/ | B | (R)
\ /--(R)--+ | |
X +------+--- OUT
/ \--(R)--+ |
|\ | B |
B --| -+------- E C -----+
|/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie

You missed the part where what I really need is two circuits, each
with input A, but one with output A and the other with output Abar,
delay to each output EQUAL.

What is your preference in dry white wine ?:-)

Unfortunately I'm on the wagon at the moment. Something untoward
going on in my colon. Colonoscopy scheduled for Tuesday. Damned
capitalist health care... 1 week delay (from Doctor's order) while I'm
weaned from anti-inflammatory which could cause bleeding ;-)


A week? It was over a year with the VA.


--
You can't fix stupid. You can't even put a Band-Aid™ on it, because it's
Teflon coated.

"Jim Thompson" wrote in
message ...
On Thu, 10 Mar 2011 22:32:55 +0100, "Arie de Muynck"
wrote:

snip

You missed the part where what I really need is two circuits, each
with input A, but one with output A and the other with output Abar,
delay to each output EQUAL.

snip

Could you possibly add a buffer in order to create a 3 stage delay?





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