Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave

"Dave" wrote in message
netamerica...
Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According
to what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?


Not strictly the answer to your question - but it isn't easy to accomodate
the spread of Idss/VGSoff with such a small headroom as 9V, you might find
that using a single (bipolar) transistor current source instead of a source
resistor works better than raising Vg above 0V.

"Dave" schreef in bericht
netamerica...
Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According
to what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




You biased the FET like an NPN transistor. Using an N-channel FET for
amplification requires the gate voltage kept below the source voltage. After
a quick glance I'd day you'll have to remove the 3M6 resistor and increase
the drain resistor to some k.

petrus bitbyter

"petrus bitbyter" wrote in message
ll.nl...

"Dave" schreef in bericht
netamerica...
Okay, like I said once before, I'm ignorant. But I am trying to fix
that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According
to what I read, Vg should be 2.65 VDC, which it does measure to be with
my Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




You biased the FET like an NPN transistor. Using an N-channel FET for
amplification requires the gate voltage kept below the source voltage.
After a quick glance I'd day you'll have to remove the 3M6 resistor and
increase the drain resistor to some k.


Some appnotes suggest an elevated Vg as a means of managing the device
spread, but its not viable with such limited headroom.

On Tue, 25 May 2010 11:51:04 -0500, "Dave" wrote:

Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




Jfets have absurd unit-to-unit variations.

Pull the fet out and measure Idss. I bet it's about 4 mA. The spec
range is 8 to 20, but with NTE one never knows...

I assume everything is connected OK. Does it amplify?

John

"John Larkin" wrote in message
...
On Tue, 25 May 2010 11:51:04 -0500, "Dave" wrote:

Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According
to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




Jfets have absurd unit-to-unit variations.

Pull the fet out and measure Idss. I bet it's about 4 mA. The spec
range is 8 to 20, but with NTE one never knows...

I assume everything is connected OK. Does it amplify?

John


Hey John, thanks for the reply. Sorry it took me so long to get back onto
this. Believe it or not I have been trying to eliminate variables and
possibilities since I posted previously.

You are right on the money, Idss is roughly 4mA. So I tried to work with
that limitation and bias the device accordingly. Please see attached
file...

On my workbench, input to the device is is a 500mV P-P 10kHz square wave,
but the device output is like 50mV. I have checked and double checked the
configuration and all connections, replacing the device when I ran out of
things to check. No change. I am posting the entire schematic, just for
complete measure, cause I am obviously missing something but have no idea
what it is. Output from the entire circuit is 500mV P-P 10kHz, so I figure
that the rest of the circuit is at least trying to overcome the deficiencies
of the first stage of pseudo-amplification. In case anyone is wondering,
the 5M trimpot is intended to eliminate the possibility of poorly chosen
values for R2, in the potential divider biasing setup. This way I can
adjust it for maximum output, if it can be called that...

Could my problem be the large values I am using for the potential divider on
the NTE451? I read that they must be quite large to avoid other problems
(slips my mind at the moment) but am now wondering. *Any* ideas are eagerly
sought. Vg measures 3.4V, and Vgs measures approx .2V, but changing these
values has no positive effect. Beginning to suspect that Ian was right, and
there just isn't enough "space" for using a JFET. Wondering if I need to
make the shift to 12VDC.

Out of other ideas...

Dave

On Fri, 28 May 2010 22:17:52 -0500, "Dave" wrote:


"John Larkin" wrote in message
.. .
On Tue, 25 May 2010 11:51:04 -0500, "Dave" wrote:

Okay, like I said once before, I'm ignorant. But I am trying to fix that.

Attempting to bias 2N5486 JFET as shown in the diagram below. According
to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




Jfets have absurd unit-to-unit variations.

Pull the fet out and measure Idss. I bet it's about 4 mA. The spec
range is 8 to 20, but with NTE one never knows...

I assume everything is connected OK. Does it amplify?

John


Hey John, thanks for the reply. Sorry it took me so long to get back onto
this. Believe it or not I have been trying to eliminate variables and
possibilities since I posted previously.

You are right on the money, Idss is roughly 4mA. So I tried to work with
that limitation and bias the device accordingly. Please see attached
file...

On my workbench, input to the device is is a 500mV P-P 10kHz square wave,
but the device output is like 50mV. I have checked and double checked the
configuration and all connections, replacing the device when I ran out of
things to check. No change. I am posting the entire schematic, just for
complete measure, cause I am obviously missing something but have no idea
what it is. Output from the entire circuit is 500mV P-P 10kHz, so I figure
that the rest of the circuit is at least trying to overcome the deficiencies
of the first stage of pseudo-amplification. In case anyone is wondering,
the 5M trimpot is intended to eliminate the possibility of poorly chosen
values for R2, in the potential divider biasing setup. This way I can
adjust it for maximum output, if it can be called that...

Could my problem be the large values I am using for the potential divider on
the NTE451? I read that they must be quite large to avoid other problems
(slips my mind at the moment) but am now wondering. *Any* ideas are eagerly
sought. Vg measures 3.4V, and Vgs measures approx .2V, but changing these
values has no positive effect. Beginning to suspect that Ian was right, and
there just isn't enough "space" for using a JFET. Wondering if I need to
make the shift to 12VDC.

Out of other ideas...

Dave



Your second stage, the bipolar thing, is running at around 100 mA.
Assuming a beta of 100, its base input impedance is ballpark 30 ohms.
That's raelly loading down the fet stage.

If the transconductance (Gm) of the fet were 0.01 siemens, the
unloaded gain would be Gm * Rl = 0.01 * 1K = 10. Load it with 30 ohms
and the gain is 0.01 * 30 = 0.3.

Something like that.

If that's an antenna on the left, the 100 ohms and the 1K pot are
going to gobble up all the signal right at the front end.

John

"flipper" wrote in message
...
On Fri, 28 May 2010 21:47:33 -0700, John Larkin
wrote:

On Fri, 28 May 2010 22:17:52 -0500, "Dave" wrote:


"John Larkin" wrote in
message
...
On Tue, 25 May 2010 11:51:04 -0500, "Dave" wrote:

Okay, like I said once before, I'm ignorant. But I am trying to fix
that.

Attempting to bias 2N5486 JFET as shown in the diagram below.
According
to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




Jfets have absurd unit-to-unit variations.

Pull the fet out and measure Idss. I bet it's about 4 mA. The spec
range is 8 to 20, but with NTE one never knows...

I assume everything is connected OK. Does it amplify?

John


Hey John, thanks for the reply. Sorry it took me so long to get back
onto
this. Believe it or not I have been trying to eliminate variables and
possibilities since I posted previously.

You are right on the money, Idss is roughly 4mA. So I tried to work with
that limitation and bias the device accordingly. Please see attached
file...

On my workbench, input to the device is is a 500mV P-P 10kHz square wave,
but the device output is like 50mV. I have checked and double checked
the
configuration and all connections, replacing the device when I ran out of
things to check. No change. I am posting the entire schematic, just for
complete measure, cause I am obviously missing something but have no idea
what it is. Output from the entire circuit is 500mV P-P 10kHz, so I
figure
that the rest of the circuit is at least trying to overcome the
deficiencies
of the first stage of pseudo-amplification. In case anyone is wondering,
the 5M trimpot is intended to eliminate the possibility of poorly chosen
values for R2, in the potential divider biasing setup. This way I can
adjust it for maximum output, if it can be called that...

Could my problem be the large values I am using for the potential divider
on
the NTE451? I read that they must be quite large to avoid other problems
(slips my mind at the moment) but am now wondering. *Any* ideas are
eagerly
sought. Vg measures 3.4V, and Vgs measures approx .2V, but changing
these
values has no positive effect. Beginning to suspect that Ian was right,
and
there just isn't enough "space" for using a JFET. Wondering if I need to
make the shift to 12VDC.

Out of other ideas...

Dave



Your second stage, the bipolar thing, is running at around 100 mA.
Assuming a beta of 100, its base input impedance is ballpark 30 ohms.
That's raelly loading down the fet stage.

If the transconductance (Gm) of the fet were 0.01 siemens, the
unloaded gain would be Gm * Rl = 0.01 * 1K = 10. Load it with 30 ohms
and the gain is 0.01 * 30 = 0.3.

Something like that.

If that's an antenna on the left, the 100 ohms and the 1K pot are
going to gobble up all the signal right at the front end.

John

Plus. the source bypass rolloff is about 13kHz and the inter stage
coupling is an order of magnitude worse.

Q1 may not even be conducting, or not much, because Vgs tolerance for
the 2N5486 extends to -6V.

Wow. God. Thank you John, and thank you Flipper. I knew if I put the
entire schematic out there, I would find out things I had no idea I was
doing wrong. I knew that I didn't really know what I was doing, but I had
no idea it was this bad. weak grin

So anyways, the things you point out describe exactly what I am seeing.
Sooo, let me try to replace the varactor with a real capacitor (getting rid
of the 100 ohm resistor and the 1K pot). I would try to eliminate the
attempt at tuning the input altogether, but am afraid of swamping the input
with 60 Hz hum. This thing is supposed to be the part of a Fox/Hound setup
that pulls a 10kHz signal out of a breaker box to indicate which breaker has
the Fox plugged into it (remember that?) Not even sure where to start with
the rest. Should I put another NTE451 in as the second stage, and use that
to drive the final two stages as shown? (Making four transistors, rather
than three.) Let me also back off on driving the NTE85 (audio preamp, can't
remember what it subs for) so hard, to make it easier for the FETs to do
their thing.

Thanks so much for the feedback and help. It's been nearly 30 years since I
was in school, and I think I've forgotten everything I knew at one time.

Take it easy...

Dave

On Sat, 29 May 2010 08:09:46 -0500, "Dave" wrote:


"flipper" wrote in message
.. .
On Fri, 28 May 2010 21:47:33 -0700, John Larkin
wrote:

On Fri, 28 May 2010 22:17:52 -0500, "Dave" wrote:


"John Larkin" wrote in
message
m...
On Tue, 25 May 2010 11:51:04 -0500, "Dave" wrote:

Okay, like I said once before, I'm ignorant. But I am trying to fix
that.

Attempting to bias 2N5486 JFET as shown in the diagram below.
According
to
what I read, Vg should be 2.65 VDC, which it does measure to be with my
Fluke. But Vs should be 5.92 or some such, and only measures 2.97,
indicating I don't have the 7 or 8 mA I expected. Vgs measures -.08VDC
which, to me, doesnt jive at all. Somebody please tell me, what am I
missing here?

Thanks,

Dave




Jfets have absurd unit-to-unit variations.

Pull the fet out and measure Idss. I bet it's about 4 mA. The spec
range is 8 to 20, but with NTE one never knows...

I assume everything is connected OK. Does it amplify?

John


Hey John, thanks for the reply. Sorry it took me so long to get back
onto
this. Believe it or not I have been trying to eliminate variables and
possibilities since I posted previously.

You are right on the money, Idss is roughly 4mA. So I tried to work with
that limitation and bias the device accordingly. Please see attached
file...

On my workbench, input to the device is is a 500mV P-P 10kHz square wave,
but the device output is like 50mV. I have checked and double checked
the
configuration and all connections, replacing the device when I ran out of
things to check. No change. I am posting the entire schematic, just for
complete measure, cause I am obviously missing something but have no idea
what it is. Output from the entire circuit is 500mV P-P 10kHz, so I
figure
that the rest of the circuit is at least trying to overcome the
deficiencies
of the first stage of pseudo-amplification. In case anyone is wondering,
the 5M trimpot is intended to eliminate the possibility of poorly chosen
values for R2, in the potential divider biasing setup. This way I can
adjust it for maximum output, if it can be called that...

Could my problem be the large values I am using for the potential divider
on
the NTE451? I read that they must be quite large to avoid other problems
(slips my mind at the moment) but am now wondering. *Any* ideas are
eagerly
sought. Vg measures 3.4V, and Vgs measures approx .2V, but changing
these
values has no positive effect. Beginning to suspect that Ian was right,
and
there just isn't enough "space" for using a JFET. Wondering if I need to
make the shift to 12VDC.

Out of other ideas...

Dave



Your second stage, the bipolar thing, is running at around 100 mA.
Assuming a beta of 100, its base input impedance is ballpark 30 ohms.
That's raelly loading down the fet stage.

If the transconductance (Gm) of the fet were 0.01 siemens, the
unloaded gain would be Gm * Rl = 0.01 * 1K = 10. Load it with 30 ohms
and the gain is 0.01 * 30 = 0.3.

Something like that.

If that's an antenna on the left, the 100 ohms and the 1K pot are
going to gobble up all the signal right at the front end.

John

Plus. the source bypass rolloff is about 13kHz and the inter stage
coupling is an order of magnitude worse.

Q1 may not even be conducting, or not much, because Vgs tolerance for
the 2N5486 extends to -6V.

Wow. God. Thank you John, and thank you Flipper. I knew if I put the
entire schematic out there, I would find out things I had no idea I was
doing wrong. I knew that I didn't really know what I was doing, but I had
no idea it was this bad. weak grin

So anyways, the things you point out describe exactly what I am seeing.
Sooo, let me try to replace the varactor with a real capacitor (getting rid
of the 100 ohm resistor and the 1K pot). I would try to eliminate the
attempt at tuning the input altogether, but am afraid of swamping the input
with 60 Hz hum. This thing is supposed to be the part of a Fox/Hound setup
that pulls a 10kHz signal out of a breaker box to indicate which breaker has
the Fox plugged into it (remember that?) Not even sure where to start with
the rest. Should I put another NTE451 in as the second stage, and use that
to drive the final two stages as shown? (Making four transistors, rather
than three.) Let me also back off on driving the NTE85 (audio preamp, can't
remember what it subs for) so hard, to make it easier for the FETs to do
their thing.

Thanks so much for the feedback and help. It's been nearly 30 years since I
was in school, and I think I've forgotten everything I knew at one time.

Take it easy...

Dave


A 10 KHz resonant LC would be a good front end. Then a fet-input opamp
maybe. That could drive a headphone directly, or maybe one more gain
stage for a speaker.

If you want to go with discretes, consider

Tuned LC

Jfet follower

audio-preamp type bipolar amp stages, low current at first.

John