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Default Digital Clock With Timer - 24HRTIMR.pdf

Since there's no schematic shown in the kit's documentation, I used the
positive power supply example at:

http://www.semiconductor-sanyo.com/ds_e/1543_d.pdf

My circuit is a 24 hour timer which starts when S1 (a momentary
pushbutton switch) is pressed, and stops 24 hours later.

It's connected directly to the LM8560's pins and gets its operating
power from the kit's power supply.

Here's how it works:

On power-up, U1-12 and 13 are held low until C1 charges up to U1D's
switching threshold.

Until then, U1D-11 is forced high, setting the latch U1A-U1B with U1-3
being forced high, and U1-4 low.

U1-3 is connected to the enable of U4, inhibiting it from counting, and
U1-4 is connected to U1-16 on the kit, which will allow its timer output
to function when the clock time equals the timer set time.

Therefore, on power-up, the override (my circuit) will be transparent to
the kit and it will function as if the override wasn't there.

Now, if S1 on the override is made, the collector of Q1 will go low and
hex 4F will be broadside loaded into U2, hex 1A into U3, and hex 00 into
U4.

Hex 4F 1A 00 is decimal 5 184 000, which is the number of 60Hz cycles in
24 hours, and when S1 is released the counter chain will start
decrementing with every 60Hz cycle until it gets to 000, which will be
24 hours after S1 is released.

The clock source for the kit is the 60Hz mains, and is also used in the
override, so after counting down 5 185 000 60Hz cycles, 24 hours will
have elapsed.

When that happens, U2, U3, and U4 will have counted all the way down to
zero and their ZD (zero detect) pins will all be low.

That will cause U1-8 and 9 to be pulled to ground through R8, and U1-10
will be forced high. That high will cause U1-6 to go high and, as on
power-up, to set the latch, which will release the inhibit on the kit
timer and keep the counter chain from counting until S1 on the override
is actuated, starting the cycle anew.



JF


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File Type: pdf 24HRTIMR.pdf (60.5 KB, 122 views)
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Default Digital Clock With Timer - 24HRTIMR.pdf - 24HRTIMR.pdf

On Mon, 26 Oct 2009 07:30:19 -0500, John Fields
wrote:

Since there's no schematic shown in the kit's documentation, I used the
positive power supply example at:

http://www.semiconductor-sanyo.com/ds_e/1543_d.pdf

My circuit is a 24 hour timer which starts when S1 (a momentary
pushbutton switch) is pressed, and stops 24 hours later.

It's connected directly to the LM8560's pins and gets its operating
power from the kit's power supply.

Here's how it works:

On power-up, U1-12 and 13 are held low until C1 charges up to U1D's
switching threshold.

Until then, U1D-11 is forced high, setting the latch U1A-U1B with U1-3
being forced high, and U1-4 low.

U1-3 is connected to the enable of U4, inhibiting it from counting, and
U1-4 is connected to U1-16 on the kit, which will allow its timer output
to function when the clock time equals the timer set time.

Therefore, on power-up, the override (my circuit) will be transparent to
the kit and it will function as if the override wasn't there.

Now, if S1 on the override is made, the collector of Q1 will go low and
hex 4F will be broadside loaded into U2, hex 1A into U3, and hex 00 into
U4.

Hex 4F 1A 00 is decimal 5 184 000, which is the number of 60Hz cycles in
24 hours, and when S1 is released the counter chain will start
decrementing with every 60Hz cycle until it gets to 000, which will be
24 hours after S1 is released.

The clock source for the kit is the 60Hz mains, and is also used in the
override, so after counting down 5 185 000 60Hz cycles, 24 hours will
have elapsed.

When that happens, U2, U3, and U4 will have counted all the way down to
zero and their ZD (zero detect) pins will all be low.

That will cause U1-8 and 9 to be pulled to ground through R8, and U1-10
will be forced high. That high will cause U1-6 to go high and, as on
power-up, to set the latch, which will release the inhibit on the kit
timer and keep the counter chain from counting until S1 on the override
is actuated, starting the cycle anew.


---
The OP requested an audio alarm when the override timed out, (which I
missed the first time around) and it's included in the attachment.

When the override times out, U1-3 will go high, disabling the counter
chain and turning on Q2, a low-side driver for the beeper, BP1, which
will sound continuously until S1 is pressed, starting a new override
cycle.

JF


Attached Files
File Type: pdf 24HRTIMR.pdf (64.7 KB, 78 views)
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