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| Electronic Schematics (alt.binaries.schematics.electronic) A place to show and share your electronics schematic drawings. |
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#1
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf
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#2
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf
On Mon, 23 Jun 2008 14:25:37 -0500, John Fields
wrote: --- Aarghhh! Rev A JF |
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#3
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf
On Mon, 23 Jun 2008 14:38:44 -0500, John Fields
wrote: On Mon, 23 Jun 2008 14:25:37 -0500, John Fields wrote: --- Aarghhh! Rev A --- LOL, there's a more or less "subtle" error (more like an inconsistency) in the drawing. can anyone spot it? JF |
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#4
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf
"John Fields" wrote in message
... LOL, there's a more or less "subtle" error (more like an inconsistency) in the drawing. can anyone spot it? It seems to me it's lacking registers so the count is only updated when the gate is off. I haven't checked what's inside all the chips. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms |
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#5
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf - 7DIGDSPLb.DWG
On Tue, 24 Jun 2008 23:48:31 -0500, "Tim Williams"
wrote: "John Fields" wrote in message .. . LOL, there's a more or less "subtle" error (more like an inconsistency) in the drawing. can anyone spot it? It seems to me it's lacking registers so the count is only updated when the gate is off. I haven't checked what's inside all the chips. --- That part's OK, and the gate time will be determined by how long ENABLE- stays low and allows the chain to accumulate clocks. For example, with a precisely 1 second long ENABLE- pulse and an input clock of 10MHz, the display should read 10000000 from left to right. The error I was referring to was that with the way the wiring is shown, for a 1s long ENABLE- pulse the display would read 0000001.  The attachment shows the fix which, BTW, discloses another error and its fix... one can't display 10000000 with seven digits. Oh well, practice makes perfect. :-) JF |
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#6
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf - 7DIGDSPLb.DWG
" --- That part's OK, and the gate time will be determined by how long ENABLE- stays low and allows the chain to accumulate clocks. For example, with a precisely 1 second long ENABLE- pulse and an input clock of 10MHz, the display should read 10000000 from left to right. The error I was referring to was that with the way the wiring is shown, for a 1s long ENABLE- pulse the display would read 0000001. The attachment shows the fix which, BTW, discloses another error and its fix... one can't display 10000000 with seven digits. Oh well, practice makes perfect. :-) JF What happened to the PDF? I can't read a DWG... I guess a flipflop on the last digit...... |
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#7
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7 DIGIT 10MHz counter (from sci.electrinics.misc) - 7DIGDSPL-Model.pdf - 7DIGDSPLa-Model.pdf - 7DIGDSPLb.DWG - 7DIGDSPLc-Model.pdf
On Thu, 26 Jun 2008 22:20:21 +0100, "TT_Man"
wrote: " --- That part's OK, and the gate time will be determined by how long ENABLE- stays low and allows the chain to accumulate clocks. For example, with a precisely 1 second long ENABLE- pulse and an input clock of 10MHz, the display should read 10000000 from left to right. The error I was referring to was that with the way the wiring is shown, for a 1s long ENABLE- pulse the display would read 0000001. The attachment shows the fix which, BTW, discloses another error and its fix... one can't display 10000000 with seven digits. Oh well, practice makes perfect. :-) JF What happened to the PDF? I can't read a DWG... I guess a flipflop on the last digit...... --- Oops... JF |
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