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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB. Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF. Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK. Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.

Caesar
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John Larkin
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

On Sat, 18 Feb 2006 10:59:10 -0500, LRCR wrote:

I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB. Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF. Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK. Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.

Caesar


A 2N7000/7002 has about 2 ohms on resistance at +5 on the gate, and 11
pF typical drain capacitance. They cost a few cents each.

John



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Ancient_Hacker
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

As an alternative, you could try using three diodes in series fed by a
Rf choke and a 100 ohm resistor., that should let any legal video
signal through, then when you apply 5 volts that should make for a
pretty low value shunt to ground.

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Klaus Kragelund
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

LRCR wrote:
I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB. Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF. Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK. Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.


What about the logic level FDV301N (6pF)

or perhaps just a plain BC847 instead of the FET (add base resistor)

Regards

Klaus

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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

I can't picture it in my mind. Can you sketch a schematic? I am very
interested.


On 18 Feb 2006 09:21:28 -0800, "Ancient_Hacker" wrote:

As an alternative, you could try using three diodes in series fed by a
Rf choke and a 100 ohm resistor., that should let any legal video
signal through, then when you apply 5 volts that should make for a
pretty low value shunt to ground.



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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)



Thanks for the info

Caesar

On Sat, 18 Feb 2006 08:52:15 -0800, John Larkin
wrote:

On Sat, 18 Feb 2006 10:59:10 -0500, LRCR wrote:

I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB. Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF. Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK. Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.

Caesar


A 2N7000/7002 has about 2 ohms on resistance at +5 on the gate, and 11
pF typical drain capacitance. They cost a few cents each.

John


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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

Thanks for the info.

Caesar
On 18 Feb 2006 16:11:29 -0800, "Klaus Kragelund"
wrote:

LRCR wrote:
I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB. Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF. Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK. Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.


What about the logic level FDV301N (6pF)

or perhaps just a plain BC847 instead of the FET (add base resistor)

Regards

Klaus

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John Jardine.
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)


"LRCR" wrote in message
...
[...]

Caesar


FET off and the output capacitance value for the suggested Fets [Coss] will
be at a maximum as there is no drain to source voltage. Best so far is the
2N7000 that could maybe run to the 20MHz mark. Also another problem in that
the negative going sync tips will start clipping.
If it could be arranged that when OFF the Fet sees a fixed bias voltage, the
Coss values can be forced low enough to offer a respectable bandwidth. Looks
like that original -5V rail had this use but 50ma is way excessive. Why not
use the +5V rail in a similar manner.?
john


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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

So John, you're saying that if I can bais the FET' Drain to Source
with the 5V while it is OFF, this will help to lower the Drain to
Source Capacitance.


Caesar

On Sat, 18 Feb 2006 18:50:54 -0800, "John Jardine."
wrote:


"LRCR" wrote in message
.. .
[...]

Caesar


FET off and the output capacitance value for the suggested Fets [Coss] will
be at a maximum as there is no drain to source voltage. Best so far is the
2N7000 that could maybe run to the 20MHz mark. Also another problem in that
the negative going sync tips will start clipping.
If it could be arranged that when OFF the Fet sees a fixed bias voltage, the
Coss values can be forced low enough to offer a respectable bandwidth. Looks
like that original -5V rail had this use but 50ma is way excessive. Why not
use the +5V rail in a similar manner.?
john


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John Jardine.
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)


"LRCR" wrote in message
...
So John, you're saying that if I can bais the FET' Drain to Source
with the 5V while it is OFF, this will help to lower the Drain to
Source Capacitance.


Caesar

[...]

Yes. (but ........
As arrangement seemed so intriguingly "simple", thought I'd run the spice
and oh-so casually figure out a working arrangement. A whole 3 hours!
later, figured the FET idea is a time waster.
Now been driven home to me the significance of the Ciss,Coss,Crss value
interactions under this linear-switching condition.
Horrible little things are constantly on the move, resulting in significant
DC shifts, signal loss variations and harmonic distortion. Tease apart one
complicated interaction and another strolls in to fill it's place.
Tried various bias arrangements but at 20MHz, the FET harmonic distortion
(5% at best), the loss of output voltage (-10% at best) and variable DC
offset shifting with signal level suggested I was on a loser.

Eventually just fitted a normal NPN small signal transistor like Kraus K
suggested (I used a BC547 and 1k base R)).
Magic ... . Distortion mostly 3rd at the 1% level. No mysterious DC shifts
and NO signal loss.
(confirmed on a spectrum analyser and tracking gen).

I enjoyed that, Ta!.
john




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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

Klaus suggested BC847. Is this the same as BC547?. Also, is there a
negative bais voltage on the emitter of NPN or is the emitter
connected to ground? So basically the circuit is


COAX 75ohm Line
video source------------------------------+----video receiver
|
|
|
R=75
|
|
C
TTL-------R=1k---B BC547
E
|
|
-V=????

By the way, I notice that when I connected a -5v to the source of the
MOSFET, I did see a DC variation. I had to connect the source of the
FET to GND in order to stop the variation. It is interest that in
your analysis that you commented that the MOSFET arrangement will have
"...significant DC shifts". Maybe the DC shifts are still in the
MOSFET arrangement with the source connected to GND, but I don't see
the shift under the GND connection condition.

Caesar

On Sun, 19 Feb 2006 11:33:04 -0800, "John Jardine."
wrote:


"LRCR" wrote in message
.. .
So John, you're saying that if I can bais the FET' Drain to Source
with the 5V while it is OFF, this will help to lower the Drain to
Source Capacitance.


Caesar

[...]

Yes. (but ........
As arrangement seemed so intriguingly "simple", thought I'd run the spice
and oh-so casually figure out a working arrangement. A whole 3 hours!
later, figured the FET idea is a time waster.
Now been driven home to me the significance of the Ciss,Coss,Crss value
interactions under this linear-switching condition.
Horrible little things are constantly on the move, resulting in significant
DC shifts, signal loss variations and harmonic distortion. Tease apart one
complicated interaction and another strolls in to fill it's place.
Tried various bias arrangements but at 20MHz, the FET harmonic distortion
(5% at best), the loss of output voltage (-10% at best) and variable DC
offset shifting with signal level suggested I was on a loser.

Eventually just fitted a normal NPN small signal transistor like Kraus K
suggested (I used a BC547 and 1k base R)).
Magic ... . Distortion mostly 3rd at the 1% level. No mysterious DC shifts
and NO signal loss.
(confirmed on a spectrum analyser and tracking gen).

I enjoyed that, Ta!.
john


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Klaus Kragelund
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)


LRCR wrote:
Klaus suggested BC847. Is this the same as BC547?


BC847 is just the SMD version of the leaded BC547 (only major
difference is the thermal resistance of the junction-case)

Regards

Klaus

. Also, is there a
negative bais voltage on the emitter of NPN or is the emitter
connected to ground? So basically the circuit is


COAX 75ohm Line
video source------------------------------+----video receiver
|
|
|
R=75
|
|
C
TTL-------R=1k---B BC547
E
|
|
-V=????

By the way, I notice that when I connected a -5v to the source of the
MOSFET, I did see a DC variation. I had to connect the source of the
FET to GND in order to stop the variation. It is interest that in
your analysis that you commented that the MOSFET arrangement will have
"...significant DC shifts". Maybe the DC shifts are still in the
MOSFET arrangement with the source connected to GND, but I don't see
the shift under the GND connection condition.

Caesar

On Sun, 19 Feb 2006 11:33:04 -0800, "John Jardine."
wrote:


"LRCR" wrote in message
.. .
So John, you're saying that if I can bais the FET' Drain to Source
with the 5V while it is OFF, this will help to lower the Drain to
Source Capacitance.


Caesar

[...]

Yes. (but ........
As arrangement seemed so intriguingly "simple", thought I'd run the spice
and oh-so casually figure out a working arrangement. A whole 3 hours!
later, figured the FET idea is a time waster.
Now been driven home to me the significance of the Ciss,Coss,Crss value
interactions under this linear-switching condition.
Horrible little things are constantly on the move, resulting in significant
DC shifts, signal loss variations and harmonic distortion. Tease apart one
complicated interaction and another strolls in to fill it's place.
Tried various bias arrangements but at 20MHz, the FET harmonic distortion
(5% at best), the loss of output voltage (-10% at best) and variable DC
offset shifting with signal level suggested I was on a loser.

Eventually just fitted a normal NPN small signal transistor like Kraus K
suggested (I used a BC547 and 1k base R)).
Magic ... . Distortion mostly 3rd at the 1% level. No mysterious DC shifts
and NO signal loss.
(confirmed on a spectrum analyser and tracking gen).

I enjoyed that, Ta!.
john


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John Jardine.
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)


"LRCR" wrote in message
...
Klaus suggested BC847. Is this the same as BC547?. Also, is there a
negative bais voltage on the emitter of NPN or is the emitter
connected to ground? So basically the circuit is


(As Klaus' reply)


COAX 75ohm Line
video source------------------------------+----video receiver
|
|
|
R=75
|
|
C
TTL-------R=1k---B BC547
E
|
|
0V


By the way, I notice that when I connected a -5v to the source of the
MOSFET, I did see a DC variation. I had to connect the source of the
FET to GND in order to stop the variation. It is interest that in
your analysis that you commented that the MOSFET arrangement will have
"...significant DC shifts". Maybe the DC shifts are still in the
MOSFET arrangement with the source connected to GND, but I don't see
the shift under the GND connection condition.

Caesar


The DC shifts were occuring due to the FET generating even harmonic
distortions due to assymetrical shifts in it's operating point at the rate
of the incoming frequency. This distortion in turn was created via the
leakage paths through the FET internals. Which in turn also depended on
series impedance in the gate driver circuit (drop the gate impedance and
then lose out on drain signal level). But, it gets messier, as the FET
starts to 'float' on it's self created DC levels which in turn alters the
operating point again. This now shifts the internal cap values and a new
cycle of leakage-distortion-operating-level change ensues. Static level
shift also happened every time the video inputs level changed. DC shift may
be only a 100mV or so but this is noticable on a video screen before the
monitor AGC has time to kick in
At 20MHz a -lot- of precious signal current is running through the FET
parasitics to ground. Not a good situation.
john


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Tony Williams
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

In article ,
LRCR wrote:
I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F
(ZETEX) and a 75 ohm resistor. Please see the BMP attachment.
The Source is connected to ground. The Drain is connected to a
75ohm resistor and the other side of the 75ohm resistor end to
the video source-to-a video analyzer coax line.

[snip]

Have you got room for a SIL reed relay?

eg, The Meder Electronic Micro SIL relay has a
footprint of about 15.2x3.9mm, about 2pF, coil to
contact, and takes less than 20mA from a 5v supply.
Switching speed is about 0.5mS. Their SIL05-xxx is
slightly larger, but takes only 10mA at 5V.

--
Tony Williams.
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Fred Bloggs
 
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Default Question regarding FET with low Drain to Source capacitance -FET_termination.jpg (0/1)




I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB.


-3dB down from what? Are you making an amplitude or impedance measurement?

Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF.


That's not right- the ZVN4106F should be something like 20pF.

Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK.


The ZVN4106F is one of the lowest available.

Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.


The problem is most likely that the video is causing some amount of
conduction through the FET body diode on the negative excursions.



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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

Tony,

Thanks for your response. Using a reed relay is not a bad idea. I
have not consider this as an option. I will have to see if I have
room on the PCB I am working on.

Thanks
Caesar

On Mon, 20 Feb 2006 11:35:46 +0000 (GMT), Tony Williams
wrote:

In article ,
LRCR wrote:
I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F
(ZETEX) and a 75 ohm resistor. Please see the BMP attachment.
The Source is connected to ground. The Drain is connected to a
75ohm resistor and the other side of the 75ohm resistor end to
the video source-to-a video analyzer coax line.

[snip]

Have you got room for a SIL reed relay?

eg, The Meder Electronic Micro SIL relay has a
footprint of about 15.2x3.9mm, about 2pF, coil to
contact, and takes less than 20mA from a 5v supply.
Switching speed is about 0.5mS. Their SIL05-xxx is
slightly larger, but takes only 10mA at 5V.


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LRCR
 
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Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

Fred,

Thank you for your response. In my setup, I use a video generator
that is capable sweeping from 1 MHz to 30MHz with an amplitude of
100IRE or 714mV. I view the sweep on a oscilloscpe and observe the
amplitude attenuation. In the case of this MOSFET design, the
attenuation of the signal goes down -3dB(Approx. 0.5v from 714mV) at
15.4MHz. Since the signal is so small across FET's drain to source
ends, it is possible that the capacitance can be high per the data
sheet. In fact where I am at on the drain to source, Coss is 75pF,
Ciss is 50pF and Crss is 30pF. The capacitance across G-D, G-S and
D-S a

Cgd = Crss = 50pF
Cgs = Ciss -Crss = 20pF
Cds = Coss - Crss = 45pF

Miller Cmout= Cgd(Av+1)/Av = 60pF with Av=1

Miller Cmin = 0 and Cgs = 0 since the source is gnd as the gate is
also ground.

Therefore,

Capacitance across the circuit where the FET's Drain to Source is
connected to:

Total Capacitance = Cmout+Cds +Cgs = 60pF+45pF+30pF = 135pF

Pretty close to what I measured, 137PF. Honestly, I was surprise with
this large number. From all the feedback I got from everyone and my
measurements, it seems that the Bipolar approach may be a better
choice. Also, from one of the feedback, John, I am also concerned
with the DC drift on the video signal that I also observed on the
video analyzer, VM700.

If you disagree with these findings, please send me your feedback
since it helps me to understandand find a proper solution to this
design.

Thanks
Caesar



On Mon, 20 Feb 2006 12:37:35 GMT, Fred Bloggs
wrote:




I am designing a switchable 75 ohm terminator circuit for a video
application using a Enhance Mode N-Channel MOSFET, ZVN4106F (ZETEX)
and a 75 ohm resistor. Please see the BMP attachment. The Source is
connected to ground. The Drain is connected to a 75ohm resistor and
the other side of the 75ohm resistor end to the video source-to-a
video analyzer coax line. The gate of the FET is connect to a TTL
source. The video source is sweeping video from 1 to 30 MHz. When the
TTL is high, the FET turns on and the analyzer sees the termination.
The frequency response is flat all the way to 30 MHz. When the TTL is
low, the FET turns off and the analyzer sees the unterminated
video,but the frequency response rolls down to 15.4MHz at -3dB.


-3dB down from what? Are you making an amplitude or impedance measurement?

Doing
my calculation using 15.4MHz, 75ohm load and fc=1/2pi*RC. The
capacitance of the FET I am using when it is off is about 137pF.


That's not right- the ZVN4106F should be something like 20pF.

Too
high for my application since I need to have a flat response within
3dB range all the way to 20MHz. I figure if I can get a low
capacitance Drain-to-source Enhance Mode N-Channel MOSFET of about
15pF or below, I'll be OK.


The ZVN4106F is one of the lowest available.

Any idea where I can find a FET like this?
By the way. In the past, someone sent me a 4 Bipolar/2 diode approach
to the switchable termination problem. This circuit worked great, but
with a cost. I need to use a -5v source that is not part of the
prototype design. The design will provide a +5v and a +12V voltage
source. Also, if i did provide a -5v souce, this source will need to
support 400mA load current since I would have to use 8 of these
switchable circuit(50mA each). Too high. The MOSFET approach on the
other hand draws very little current and can use an only +5v design
scheme. So I have to make the MOSFET approach to work, 1 to 20MHz
flatness. Any idea will be helpful.


The problem is most likely that the video is causing some amount of
conduction through the FET body diode on the negative excursions.


  #18   Report Post  
Posted to sci.electronics.design,alt.electronics,sci.electronics.components
Fred Bloggs
 
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Default Question regarding FET with low Drain to Source capacitance -FET_termination.jpg (0/1)



LRCR wrote:
Fred,

Thank you for your response. In my setup, I use a video generator
that is capable sweeping from 1 MHz to 30MHz with an amplitude of
100IRE or 714mV. I view the sweep on a oscilloscpe and observe the
amplitude attenuation. In the case of this MOSFET design, the
attenuation of the signal goes down -3dB(Approx. 0.5v from 714mV) at
15.4MHz. Since the signal is so small across FET's drain to source
ends, it is possible that the capacitance can be high per the data
sheet. In fact where I am at on the drain to source, Coss is 75pF,
Ciss is 50pF and Crss is 30pF. The capacitance across G-D, G-S and
D-S a

Cgd = Crss = 50pF Cgs = Ciss -Crss = 20pF Cds = Coss - Crss = 45pF

Miller Cmout= Cgd(Av+1)/Av = 60pF with Av=1

Miller Cmin = 0 and Cgs = 0 since the source is gnd as the gate is
also ground.

Therefore,

Capacitance across the circuit where the FET's Drain to Source is
connected to:

Total Capacitance = Cmout+Cds +Cgs = 60pF+45pF+30pF = 135pF

Pretty close to what I measured, 137PF. Honestly, I was surprise
with this large number. From all the feedback I got from everyone
and my measurements, it seems that the Bipolar approach may be a
better choice. Also, from one of the feedback, John, I am also
concerned with the DC drift on the video signal that I also observed
on the video analyzer, VM700.

If you disagree with these findings, please send me your feedback
since it helps me to understandand find a proper solution to this
design.

Thanks Caesar

That Aromat AQY221 in WH's post looks like just the thing- and fully
characterized to 10MHz- looks to have slow rolloff beyond that.

  #19   Report Post  
Posted to sci.electronics.design,alt.electronics,sci.electronics.components
LRCR
 
Posts: n/a
Default Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

Thanks Fred. I will check on this part.

Caesar

On Mon, 20 Feb 2006 16:13:49 GMT, Fred Bloggs
wrote:



LRCR wrote:
Fred,

Thank you for your response. In my setup, I use a video generator
that is capable sweeping from 1 MHz to 30MHz with an amplitude of
100IRE or 714mV. I view the sweep on a oscilloscpe and observe the
amplitude attenuation. In the case of this MOSFET design, the
attenuation of the signal goes down -3dB(Approx. 0.5v from 714mV) at
15.4MHz. Since the signal is so small across FET's drain to source
ends, it is possible that the capacitance can be high per the data
sheet. In fact where I am at on the drain to source, Coss is 75pF,
Ciss is 50pF and Crss is 30pF. The capacitance across G-D, G-S and
D-S a

Cgd = Crss = 50pF Cgs = Ciss -Crss = 20pF Cds = Coss - Crss = 45pF

Miller Cmout= Cgd(Av+1)/Av = 60pF with Av=1

Miller Cmin = 0 and Cgs = 0 since the source is gnd as the gate is
also ground.

Therefore,

Capacitance across the circuit where the FET's Drain to Source is
connected to:

Total Capacitance = Cmout+Cds +Cgs = 60pF+45pF+30pF = 135pF

Pretty close to what I measured, 137PF. Honestly, I was surprise
with this large number. From all the feedback I got from everyone
and my measurements, it seems that the Bipolar approach may be a
better choice. Also, from one of the feedback, John, I am also
concerned with the DC drift on the video signal that I also observed
on the video analyzer, VM700.

If you disagree with these findings, please send me your feedback
since it helps me to understandand find a proper solution to this
design.

Thanks Caesar

That Aromat AQY221 in WH's post looks like just the thing- and fully
characterized to 10MHz- looks to have slow rolloff beyond that.


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