On Sun, 27 Nov 2011 09:31:43 -0800, Joerg
wrote:

snip

The apparent change was due to the shift of the waveform on the
display. It was a positive pulse waveform that shifted down-screen
when AC coupled.


Ok, then I misunderstood. Now it sounds less like layout and more like
sub-optimal analog circuitry.

[...]


At the same time, the on-board ppk measurement increases
proportionally solely due to screen positioning. The overshot waveform
measures less ppk. Delta 70mV in a 2V measurement. This in the
opposite sense to the presented distortion.

How do they do it?

Sounds more and more like they do the offset before the ADC and the
analog circuitry was done by a rookie :-)


Why do they do it?

It is probably not intentional and they either didn't notice or ignored it.

I suppose that screen offsets have to be physically enforced as a DC
component introduced before the ADC, as the coding expires at the
display limits ( this evidenced by manipulating math functions to
overdiven signals )

The unipolarity of effect suggests that the ADC is seeing a unipolar
input - perhaps a protection network's capacitance is being modulated
by this shift.


Now it really sounds like an analog circuit issue in there.


I would have thought, however that internal measurements of ppk would
be generated from ADC output, and this demonstratedly cannot be the
case, if the GUI display is unaltered from the ADC output.


I would be very surprised if they didn't take the cheap route and do it
off of the ADC output. Who knows what the software does.


Input protection is specified at 35V levels, and +/-20V levels are
expected. The behavior is visible using the unipolar 2Vppk square wave
signal provided as calibration, by the device.

Anyone else see this effect on other models of similar devices?

I've only been working with this one for two days.


It's time to take a 2nd analog scope and probe around in there. I
suspect the analog DC offset changes some junction capacitance and they
do not correct for that in SW. Or worse, haven't noticed ...

If this is indeed the case then probing around with an analog scope
should bring out the truth rather quickly.

I've thrown away the warranty, for what it's worth, and given the
circuit a quick look.

After the input attenuator, a DC shift is introduced before the DAC,
as expected, to provide a unipolar ADC input and to control the screen
centering position. There's no sign of alterations in rise-time or
overshoo on either side of the buffer feeding the ADC, as the DC shift
is modulated.

At the same time, these errors are visible on the PC display.

The protection network is composed of the CB junction of a vhf bipolar
transistor to the +3V5 rail (~1pF), and a DO214(SMA) diode body to the
common return. This diode is soldered manually and is marked with the
signature (RD)found on all of
-a 54V transil,(~120pF)
-an 18V transil (~470pF)
-a conventional 200V rectifier (10-7pF)
-others?

One thing that wasn't noticed before, is that the effect is most
pronounced on channel 2 ( the channel used to demonstrate in the
images posted on a.b.s.e.). The effect on channel 1 is probably small
enough to have been ignored by a bored operator.

The ADCs are identity-ground-off. There's a nasty void in the one used
for channel 2, probably caused by metallic grit accidentally included
in the grinding operation. Some of this metal is imbedded in the void.
Image on a.b.s.e..

RL

On Mon, 28 Nov 2011 22:15:37 -0500, legg wrote:

On Sun, 27 Nov 2011 09:31:43 -0800, Joerg

The ADCs are identity-ground-off. There's a nasty void in the one used
for channel 2, probably caused by metallic grit accidentally included
in the grinding operation. Some of this metal is imbedded in the void.
Image on a.b.s.e..

The part is actually a DPDT video switch, not an ADC.

RL