Here's how it works:

U5 and U6 are 8 bit serial-in parallel-out shift registers and are used
to convert serial data appearing at U5-14 into a 16 pit parallel word
appearing on the Q outputs of U5 and U6, with the LSB rightmost.

That word is broadside loaded into U1, U2, U3, and U4, four 4 bit binary
up/down counters, the outputs of which feed the digital data inputs of
U9, a 16 bit current-output DAC.

The 5 volt reference for the DAC is generated by U8, inverted by U11A,
and then inverted again by U11B which is used to convert the current
output from U9 into a voltage which varies in steps of 76.295 microvolts
for each increment or decrement of the counter chain.

That stepped output from U11B is fed to the inputs of two comparators
which are used to determine the limits and direction of the of the ramp
generated by the DAC, like this:

First, assume that the output of R4 has been set to 4.8 volts, that the
output of R5 has been set to 2.0 volts, and that the counter chain is
counting up.

That means that U7-4 will be low and that the output of U11B will be
rising. When it gets to 4.8 volts, U12-1 will go high, setting the RS
latch U7A - U7B, forcing U7-4 high.

When that happens the count direction will be changed and the voltage
into the comparators will fall until it gets to 2.0 volts, at which
point the latch will be reset, U7-4 will go low, and the counter will
start counting up again, beginning the cycle anew.

So, R4 and R5 are used to adjust the limits, and the counter's clock is
used to adjust the slope.

JF