"Dave" wrote in message
netamerica...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT (configured
for Common Emitter) to do this, but I am in the dark as to how this might
be accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now
all my varactors are blown and I may have damaged one or more transistors.
Will be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in Vdd
headroom, I'm wondering why you feed the gate with a divider instead of a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small signal
MOSFET with a bipolar transistor regulating the bias by sensing source
current - the gain will be huge compared to a JFET so you can cancel some of
the higher input capacitance by splitting the source resistor in two and
only decoupling the resistor that senses DC source current.