Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long as
the batteries are fresh, but as they begin to wane Vgs surpasses Pinch-Off
(which is 4.0 volts for the JFET I am using, while I try to hold it at 3.95
VDC.) It has been suggested that I use a BJT (configured for Common
Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave



Forgot to mention or specify: Id is limited to 3 mA for the NTE451. Thus
the note about Vs being 9.6 VDC in the schematic.

Dave

On Thu, 19 May 2011 09:02:42 -0500, "Dave" wrote:


"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave



Forgot to mention or specify: Id is limited to 3 mA for the NTE451. Thus
the note about Vs being 9.6 VDC in the schematic.

Dave


Let's back up a bit and ask a few questions...

Is the object to firmly set NTE451 Id bias at 3mA?

What is the useful range of battery (17V) voltage?

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Thu, 19 May 2011 08:49:14 -0700, Jim Thompson
wrote:

On Thu, 19 May 2011 09:02:42 -0500, "Dave" wrote:


"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave



Forgot to mention or specify: Id is limited to 3 mA for the NTE451. Thus
the note about Vs being 9.6 VDC in the schematic.

Dave


Let's back up a bit and ask a few questions...

Is the object to firmly set NTE451 Id bias at 3mA?

What is the useful range of battery (17V) voltage?

...Jim Thompson

12V once I zoomed in ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Thu, 19 May 2011 08:58:48 -0500, "Dave" wrote:

Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long as
the batteries are fresh, but as they begin to wane Vgs surpasses Pinch-Off
(which is 4.0 volts for the JFET I am using, while I try to hold it at 3.95
VDC.) It has been suggested that I use a BJT (configured for Common
Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave


See attachment

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now all
my varactors are blown and I may have damaged one or more transistors. Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

Thanks.

Dave

On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:


"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now all
my varactors are blown and I may have damaged one or more transistors. Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

Thanks.

Dave


With the wild-spec on pinch-off the current mirror approach tightens
things up, provided no more than ~4V of source-lift is required to
reach equilibrium.

Have fun!

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Single reply at the bottom...

"flipper" wrote in message
...
On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:

Once you get it repaired reconsider the original problem statement

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the
following BJTs while keeping Vgs very near Pinch-Off.

Why are you trying to keep it near pinch off? At any rate, your
circuit wont'. It can't. You're biasing the gate and the jFET source
will settle at whatever Vgs produces a counter acting current, hence
source voltage, through the source resistor. That's why it sits at
9.6V.


Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold
it at 3.95 VDC.)

I don't know what symptom you're seeing but it shouldn't be the jFET
going into pinch off because the source voltage will simply change to
keep current flowing. You can't 'pinch it off' from gate bias because
it takes 4V (assuming that's Vgs pinch off) to do it, which means
there'd have to be at least 4V across the 3.2k, for 1.25mA (which is
clearly not pinched off), even if gate bias were 0. It clearly takes
even more current with gate positive and to pinch it off by the gate
you'd need a negative voltage source.

The jFET bias will fail when Vcc drops too low for the source voltage
to be generated, which would be around 7.5V, not from pinch off but
saturation. The signal will be clipped before that.

To explain (ignoring L4 DCR, jFET Rdson for simplicity), at 7.5V Vcc
the gate bias would be 3.525V and it takes 4 more volts (Vgs) on the
source, or 7.525V, for things to balance out but 7.525V cannot be
achieved with Vcc at 7.5V. So the jFET is biased 'full on', saturated,
trying to draw enough current to bring the source up to a voltage it
cannot get to.



It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now
all
my varactors are blown and I may have damaged one or more transistors.
Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.

It's your circuit that sets Ids and, as drawn, you have, at DC, a
crude constant current source set by (Vg+Vgs)/3200.

One problem with jFETs is the wide variation in Vgs makes them
difficult to bias with simple resistor networks. For example, Vgs on
that NTE451 ranges from .5V to 4V so if you swap in another one it
might end up drawing 1.9mA (which is a much smaller variation than the
8 to 1 Vgs range due to the crude 'current regulation' of the
degenerative 3200 Ohm resistor).

You could increase Vg to get more current, but that makes the 'low'
Vcc problem worse. Or you could lower the 3200 Ohm resistor but that
makes 'current regulation' worse.

A CCS under the source solves a number of sins by automatically
setting Vs at whatever it takes to cause that current to flow, with
the caveat Vg+Vgs(min) has to be high enough to cover the minimum
voltage drop across the type of CCS you use. A BJT current mirror is
good for that since they can operate down to Vce(sat) but I think a
degenerative emitter resistor is a good idea, especially for discrete
versions.

The current source JT posted is the same as I was thinking but,
considering the 'low Vcc' problem, you should probably lower your gate
bias voltage... and the emitter resistor a corresponding amount (more
if you want to increase Ids).

Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

Thanks.

Dave


Man, thank you for the huge amount of input to process and digest. I'm
printing this to take back to my workshop for referrence, and so I don't
have to rely on my memory as to what all you said. One thing- please
correct me if I'm wrong, but I thought that pinch-off was when Vgs exceeded
minus 4VDC (for this JFET). And that was determined by subtracting Vg from
Vs (think I have that right.) Is this not correct?

Thanks again for the helpfull reply. I am honestly learning this as I go
along and don't mean to simply waste your time. Oh, and I was trying to
bias near pinch-off because I thought that this provided greater
amplification of the signal. Now I look at it and suspect that this is not
the case. That is why I was attempting to modify the bias on the JFET when
I blew the varactors.

Take it easy...

Dave


Dave

On Fri, 20 May 2011 08:35:30 -0500, "Dave" wrote:

Single reply at the bottom...

"flipper" wrote in message
.. .
On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:

Once you get it repaired reconsider the original problem statement

"Dave" wrote in message
news Am trying to bias the JFET in the attached schematic to feed signal to
the
following BJTs while keeping Vgs very near Pinch-Off.

Why are you trying to keep it near pinch off? At any rate, your
circuit wont'. It can't. You're biasing the gate and the jFET source
will settle at whatever Vgs produces a counter acting current, hence
source voltage, through the source resistor. That's why it sits at
9.6V.


Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold
it at 3.95 VDC.)

I don't know what symptom you're seeing but it shouldn't be the jFET
going into pinch off because the source voltage will simply change to
keep current flowing. You can't 'pinch it off' from gate bias because
it takes 4V (assuming that's Vgs pinch off) to do it, which means
there'd have to be at least 4V across the 3.2k, for 1.25mA (which is
clearly not pinched off), even if gate bias were 0. It clearly takes
even more current with gate positive and to pinch it off by the gate
you'd need a negative voltage source.

The jFET bias will fail when Vcc drops too low for the source voltage
to be generated, which would be around 7.5V, not from pinch off but
saturation. The signal will be clipped before that.

To explain (ignoring L4 DCR, jFET Rdson for simplicity), at 7.5V Vcc
the gate bias would be 3.525V and it takes 4 more volts (Vgs) on the
source, or 7.525V, for things to balance out but 7.525V cannot be
achieved with Vcc at 7.5V. So the jFET is biased 'full on', saturated,
trying to draw enough current to bring the source up to a voltage it
cannot get to.



It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now
all
my varactors are blown and I may have damaged one or more transistors.
Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.

It's your circuit that sets Ids and, as drawn, you have, at DC, a
crude constant current source set by (Vg+Vgs)/3200.

One problem with jFETs is the wide variation in Vgs makes them
difficult to bias with simple resistor networks. For example, Vgs on
that NTE451 ranges from .5V to 4V so if you swap in another one it
might end up drawing 1.9mA (which is a much smaller variation than the
8 to 1 Vgs range due to the crude 'current regulation' of the
degenerative 3200 Ohm resistor).

You could increase Vg to get more current, but that makes the 'low'
Vcc problem worse. Or you could lower the 3200 Ohm resistor but that
makes 'current regulation' worse.

A CCS under the source solves a number of sins by automatically
setting Vs at whatever it takes to cause that current to flow, with
the caveat Vg+Vgs(min) has to be high enough to cover the minimum
voltage drop across the type of CCS you use. A BJT current mirror is
good for that since they can operate down to Vce(sat) but I think a
degenerative emitter resistor is a good idea, especially for discrete
versions.

The current source JT posted is the same as I was thinking but,
considering the 'low Vcc' problem, you should probably lower your gate
bias voltage... and the emitter resistor a corresponding amount (more
if you want to increase Ids).

Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

Thanks.

Dave


Man, thank you for the huge amount of input to process and digest. I'm
printing this to take back to my workshop for referrence, and so I don't
have to rely on my memory as to what all you said. One thing- please
correct me if I'm wrong, but I thought that pinch-off was when Vgs exceeded
minus 4VDC (for this JFET). And that was determined by subtracting Vg from
Vs (think I have that right.) Is this not correct?

Thanks again for the helpfull reply. I am honestly learning this as I go
along and don't mean to simply waste your time. Oh, and I was trying to
bias near pinch-off because I thought that this provided greater
amplification of the signal. Now I look at it and suspect that this is not
the case. That is why I was attempting to modify the bias on the JFET when
I blew the varactors.

Take it easy...

Dave


Dave


From the JFET datasheet, VCB of the NPN would be worst-case 0V, which
is no problem at all... for those of us who actually understand
transistors ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

"Dave" wrote in message
netamerica...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT (configured
for Common Emitter) to do this, but I am in the dark as to how this might
be accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now
all my varactors are blown and I may have damaged one or more transistors.
Will be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in Vdd
headroom, I'm wondering why you feed the gate with a divider instead of a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small signal
MOSFET with a bipolar transistor regulating the bias by sensing source
current - the gain will be huge compared to a JFET so you can cancel some of
the higher input capacitance by splitting the source resistor in two and
only decoupling the resistor that senses DC source current.

"Ian Field" wrote in message
...

"Dave" wrote in message
netamerica...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT
(configured for Common Emitter) to do this, but I am in the dark as to
how this might be accomplished. ANY help would be greatly
appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor
D4 out of utter carelessness and too much wire where it wasn't needed.
Now all my varactors are blown and I may have damaged one or more
transistors. Will be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451
apparently limits Id to 3mA by itself (much to my frustration). I don't
need to do that for it. What I do have to do is work with the 3mA it
allows. Anyway, I appreciate your input and may be back later if what
I was trying doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in Vdd
headroom, I'm wondering why you feed the gate with a divider instead of a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small signal
MOSFET with a bipolar transistor regulating the bias by sensing source
current - the gain will be huge compared to a JFET so you can cancel some
of the higher input capacitance by splitting the source resistor in two
and only decoupling the resistor that senses DC source current.


Huuuh. Thank you for the intriguing thought on a different approach. Any
ideas on where I would look for an appropriate part number? Honestly
suspected a MOSFET was maybe a better idea, but didn't know where to start
with that. And JT has already provided some details on using a BJT to sense
source current that sounds like what you are speaking of.

Thanks,

Dave

"flipper" wrote in message
...
On Fri, 20 May 2011 08:35:30 -0500, "Dave" wrote:

Single reply at the bottom...

"flipper" wrote in message
. ..
On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:

Once you get it repaired reconsider the original problem statement

"Dave" wrote in message
news Am trying to bias the JFET in the attached schematic to feed signal to
the
following BJTs while keeping Vgs very near Pinch-Off.

Why are you trying to keep it near pinch off? At any rate, your
circuit wont'. It can't. You're biasing the gate and the jFET source
will settle at whatever Vgs produces a counter acting current, hence
source voltage, through the source resistor. That's why it sits at
9.6V.


Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold
it at 3.95 VDC.)

I don't know what symptom you're seeing but it shouldn't be the jFET
going into pinch off because the source voltage will simply change to
keep current flowing. You can't 'pinch it off' from gate bias because
it takes 4V (assuming that's Vgs pinch off) to do it, which means
there'd have to be at least 4V across the 3.2k, for 1.25mA (which is
clearly not pinched off), even if gate bias were 0. It clearly takes
even more current with gate positive and to pinch it off by the gate
you'd need a negative voltage source.

The jFET bias will fail when Vcc drops too low for the source voltage
to be generated, which would be around 7.5V, not from pinch off but
saturation. The signal will be clipped before that.

To explain (ignoring L4 DCR, jFET Rdson for simplicity), at 7.5V Vcc
the gate bias would be 3.525V and it takes 4 more volts (Vgs) on the
source, or 7.525V, for things to balance out but 7.525V cannot be
achieved with Vcc at 7.5V. So the jFET is biased 'full on', saturated,
trying to draw enough current to bring the source up to a voltage it
cannot get to.



It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might
be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

Okay, Murphy's Law rules. Was effecting a minor change in the biasing
of
the JFET and when I hooked it all back up I let +12VDC hit the varactor
D4
out of utter carelessness and too much wire where it wasn't needed. Now
all
my varactors are blown and I may have damaged one or more transistors.
Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451
apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.

It's your circuit that sets Ids and, as drawn, you have, at DC, a
crude constant current source set by (Vg+Vgs)/3200.

One problem with jFETs is the wide variation in Vgs makes them
difficult to bias with simple resistor networks. For example, Vgs on
that NTE451 ranges from .5V to 4V so if you swap in another one it
might end up drawing 1.9mA (which is a much smaller variation than the
8 to 1 Vgs range due to the crude 'current regulation' of the
degenerative 3200 Ohm resistor).

You could increase Vg to get more current, but that makes the 'low'
Vcc problem worse. Or you could lower the 3200 Ohm resistor but that
makes 'current regulation' worse.

A CCS under the source solves a number of sins by automatically
setting Vs at whatever it takes to cause that current to flow, with
the caveat Vg+Vgs(min) has to be high enough to cover the minimum
voltage drop across the type of CCS you use. A BJT current mirror is
good for that since they can operate down to Vce(sat) but I think a
degenerative emitter resistor is a good idea, especially for discrete
versions.

The current source JT posted is the same as I was thinking but,
considering the 'low Vcc' problem, you should probably lower your gate
bias voltage... and the emitter resistor a corresponding amount (more
if you want to increase Ids).

Anyway, I appreciate your input and may be back later if what I was
trying
doesn't work to my satisfaction.

Thanks.

Dave


Man, thank you for the huge amount of input to process and digest. I'm
printing this to take back to my workshop for referrence, and so I don't
have to rely on my memory as to what all you said. One thing- please
correct me if I'm wrong, but I thought that pinch-off was when Vgs
exceeded
minus 4VDC (for this JFET). And that was determined by subtracting Vg
from
Vs (think I have that right.) Is this not correct?

Well, short answer is yes but

You knew there'd be a "but," didn't you?

But you're not controlling Vgs, at least not how I gather you think
you are. As I mentioned above, you are setting Vg and then the jFET,
by means of the 3200 Ohm resistor, is automagically setting Vs to
whatever it need be so that the resultant Vgs causes just the right
amount of current flow through the 3200 Ohm resistor to back bias the
source. It's a feedback circuit. Ids rises until it produces just
enough Vs and if Ids tries to rise even higher then Vs rises to
counteract it, and vice versa. It therefore 'balances' at the precise
point that Vs, due to current through the 3200 Ohm resistor, makes Vgs
just right to conduct the current needed through the 3200 Ohm
resistor.

It's called "self bias, because the jFET 'does it to itself' (with the
help of the resistor). Self bias was also quite popular with vacuum
tubes as they work the same way or, rather, a jFET works a lot like a
vacuum tube.

(The capacitor around the 3200 Ohm resistor lets RF bypass the
resistor so that feedback doesn't reduce the gain).

So, yes, more than (-)4V, or whatever the pinch off voltage is, will
pinch it off. And yes, you 'measure' it by Vg-Vs ---at the specified
pinch off current---. However, what you're measuring in the circuit
is not pinch off but, rather, the Vgs which causes 3mA (if that's what
it is) to flow through the 3200 Ohm resistor.

To 'force' pinch off you'd have to affirmatively fix both Vg and Vs to
specific values, and not let Vs 'be whatever it wants', but, for your
circuit, there'd be no real purpose in doing so.

Thanks again for the helpfull reply. I am honestly learning this as I go
along and don't mean to simply waste your time. Oh, and I was trying to
bias near pinch-off because I thought that this provided greater
amplification of the signal.

Generally not as transconductance (gain) increases with Ids and pinch
off is pretty close to no Ids. It depends on the device and where you
are on the curves but 10 times the current might get you, oh say, 2.5
times the transconductance.

Having said that don't forget that Vgs varies all over the place from
device to device so design one 'on the edge' and the next one produces
smoke curls because it's lower Vgs over currents the thing (another
reason for CCS bias).

A good general rule to keep in mind is all parameters uniformly
conspire to defeat whatever goal you're trying to achieve (Murphy's
Law, corollary 127, a usually true joke, double entendre intended.).

Now I look at it and suspect that this is not
the case. That is why I was attempting to modify the bias on the JFET
when
I blew the varactors.

Trust me, you're not the first one to blow a circuit on the bench.
We've all been there, done that, got the charcoal to prove it.

Btw, I should add to that previous discussion about bias failing at
7.5V. As indicated that was a rough illustrative example ignoring some
parameters and RF jFETs usually need a volt or two across them before
the curves flatten out. It depends on bias and, unfortunately, the
NTE451 datasheet doesn't give any curve at all so I can't say for sure
but it might take as much as 10V for things to bias up properly in
your original circuit. That doesn't alter the problem being saturation
rather than pinch off, just means it happens at a higher voltage than
the simplified example.


Take it easy...

Dave


Dave


Man. Thank you. Don't know what else to say. Thanks bunches.

Dave

"Dave" wrote in message
netamerica...

"Ian Field" wrote in message
...

"Dave" wrote in message
netamerica...

"Dave" wrote in message
news Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine
as long as the batteries are fresh, but as they begin to wane Vgs
surpasses Pinch-Off (which is 4.0 volts for the JFET I am using, while
I try to hold it at 3.95 VDC.) It has been suggested that I use a BJT
(configured for Common Emitter) to do this, but I am in the dark as to
how this might be accomplished. ANY help would be greatly
appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing
of the JFET and when I hooked it all back up I let +12VDC hit the
varactor D4 out of utter carelessness and too much wire where it wasn't
needed. Now all my varactors are blown and I may have damaged one or
more transistors. Will be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451
apparently limits Id to 3mA by itself (much to my frustration). I don't
need to do that for it. What I do have to do is work with the 3mA it
allows. Anyway, I appreciate your input and may be back later if what
I was trying doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in Vdd
headroom, I'm wondering why you feed the gate with a divider instead of a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small signal
MOSFET with a bipolar transistor regulating the bias by sensing source
current - the gain will be huge compared to a JFET so you can cancel some
of the higher input capacitance by splitting the source resistor in two
and only decoupling the resistor that senses DC source current.


Huuuh. Thank you for the intriguing thought on a different approach. Any
ideas on where I would look for an appropriate part number? Honestly
suspected a MOSFET was maybe a better idea, but didn't know where to start
with that. And JT has already provided some details on using a BJT to
sense source current that sounds like what you are speaking of.


One trick is to use 2 JFETs, one of which has its gate connected to source
and passes Idss, that gives you a current source instead of the source
resistor - unfortunately Idss spread between devices of the same type can be
pretty wide giveing not quite the resuts you were hoping for.

A more repeatable alternative is the single transistor current source in the
JFET source lead, bias the base with 2x Si diode or a LED with an
appropriate pull up resistor from Vdd, the emitter goes to Vss via a
(relatively) low value resistor which determines the collector current.

With some JFETs, Vgs-off can have a wide spread which can make difficulties
if you don't have a lot of Vdd headroom.

You can use a portion of the source current to control a BJT which sets the
MOSFET bias point, the input resistance is then determined by the bootstrap
resistor connecting the MOSFET gate to the collector/pullup resistor. The
source current sensing resistor should be adequately decoupled and it
doesn't hurt to put a small capacitor to smooth the collector.

The MOSFET has higher input capacitance than the JFET but it also has much
higher gain, you can cancel most of the capacitance by inserting a
degenerative feedback resistor between the current sense resistor and
source, this sacrifices gain and you set this to more like what you'd expect
from a JFET.

"flipper" wrote in message
...
On Fri, 20 May 2011 20:00:14 +0100, "Ian Field"
wrote:


"Dave" wrote in message
ernetamerica...

"Ian Field" wrote in message
...

"Dave" wrote in message
netamerica...

"Dave" wrote in message
news Am trying to bias the JFET in the attached schematic to feed signal
to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine
as long as the batteries are fresh, but as they begin to wane Vgs
surpasses Pinch-Off (which is 4.0 volts for the JFET I am using,
while
I try to hold it at 3.95 VDC.) It has been suggested that I use a
BJT
(configured for Common Emitter) to do this, but I am in the dark as
to
how this might be accomplished. ANY help would be greatly
appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing
of the JFET and when I hooked it all back up I let +12VDC hit the
varactor D4 out of utter carelessness and too much wire where it
wasn't
needed. Now all my varactors are blown and I may have damaged one or
more transistors. Will be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451
apparently limits Id to 3mA by itself (much to my frustration). I
don't
need to do that for it. What I do have to do is work with the 3mA it
allows. Anyway, I appreciate your input and may be back later if
what
I was trying doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in Vdd
headroom, I'm wondering why you feed the gate with a divider instead of
a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small signal
MOSFET with a bipolar transistor regulating the bias by sensing source
current - the gain will be huge compared to a JFET so you can cancel
some
of the higher input capacitance by splitting the source resistor in two
and only decoupling the resistor that senses DC source current.


Huuuh. Thank you for the intriguing thought on a different approach.
Any
ideas on where I would look for an appropriate part number? Honestly
suspected a MOSFET was maybe a better idea, but didn't know where to
start
with that. And JT has already provided some details on using a BJT to
sense source current that sounds like what you are speaking of.


One trick is to use 2 JFETs, one of which has its gate connected to source
and passes Idss, that gives you a current source instead of the source
resistor - unfortunately Idss spread between devices of the same type can
be
pretty wide giveing not quite the resuts you were hoping for.

A more repeatable alternative is the single transistor current source in
the
JFET source lead, bias the base with 2x Si diode or a LED with an
appropriate pull up resistor from Vdd, the emitter goes to Vss via a
(relatively) low value resistor which determines the collector current.

With some JFETs, Vgs-off can have a wide spread which can make
difficulties
if you don't have a lot of Vdd headroom.

You can use a portion of the source current to control a BJT which sets
the
MOSFET bias point, the input resistance is then determined by the
bootstrap
resistor connecting the MOSFET gate to the collector/pullup resistor. The
source current sensing resistor should be adequately decoupled and it
doesn't hurt to put a small capacitor to smooth the collector.

The MOSFET has higher input capacitance than the JFET but it also has much
higher gain, you can cancel most of the capacitance by inserting a
degenerative feedback resistor between the current sense resistor and
source, this sacrifices gain and you set this to more like what you'd
expect
from a JFET.


Well, as far as Vdd headroom goes it's not so much the spread as Vgs
max and I'm not sure you're much, if any, better off selecting a
MOSFET than a jFET.

Well I suppose if you used a high voltage MOSFET from a SMPSU that had a
Vgs-thr in the direction of 6 - 8V it might get a bit tricky, might not do
too well at the frequency range suggested by the inductances in the OPs
design either.

"flipper" wrote in message
...
On Sat, 21 May 2011 14:16:32 +0100, "Ian Field"
wrote:


"flipper" wrote in message
. ..
On Fri, 20 May 2011 20:00:14 +0100, "Ian Field"
wrote:


"Dave" wrote in message
nternetamerica...

"Ian Field" wrote in message
...

"Dave" wrote in message
netamerica...

"Dave" wrote in message
news Am trying to bias the JFET in the attached schematic to feed signal
to
the following BJTs while keeping Vgs very near Pinch-Off. Works
fine
as long as the batteries are fresh, but as they begin to wane Vgs
surpasses Pinch-Off (which is 4.0 volts for the JFET I am using,
while
I try to hold it at 3.95 VDC.) It has been suggested that I use a
BJT
(configured for Common Emitter) to do this, but I am in the dark as
to
how this might be accomplished. ANY help would be greatly
appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the
biasing
of the JFET and when I hooked it all back up I let +12VDC hit the
varactor D4 out of utter carelessness and too much wire where it
wasn't
needed. Now all my varactors are blown and I may have damaged one or
more transistors. Will be back later after I have sorted all this
out.

JT: Thanks for the input on the source resistor, but the NTE451
apparently limits Id to 3mA by itself (much to my frustration). I
don't
need to do that for it. What I do have to do is work with the 3mA
it
allows. Anyway, I appreciate your input and may be back later if
what
I was trying doesn't work to my satisfaction.

If you're having trouble stabilising the bias against reduction in
Vdd
headroom, I'm wondering why you feed the gate with a divider instead
of
a
simple "gate leak" resistor.

If the frequency isn't too high you might get away with a small
signal
MOSFET with a bipolar transistor regulating the bias by sensing
source
current - the gain will be huge compared to a JFET so you can cancel
some
of the higher input capacitance by splitting the source resistor in
two
and only decoupling the resistor that senses DC source current.


Huuuh. Thank you for the intriguing thought on a different approach.
Any
ideas on where I would look for an appropriate part number? Honestly
suspected a MOSFET was maybe a better idea, but didn't know where to
start
with that. And JT has already provided some details on using a BJT to
sense source current that sounds like what you are speaking of.


One trick is to use 2 JFETs, one of which has its gate connected to
source
and passes Idss, that gives you a current source instead of the source
resistor - unfortunately Idss spread between devices of the same type
can
be
pretty wide giveing not quite the resuts you were hoping for.

A more repeatable alternative is the single transistor current source in
the
JFET source lead, bias the base with 2x Si diode or a LED with an
appropriate pull up resistor from Vdd, the emitter goes to Vss via a
(relatively) low value resistor which determines the collector current.

With some JFETs, Vgs-off can have a wide spread which can make
difficulties
if you don't have a lot of Vdd headroom.

You can use a portion of the source current to control a BJT which sets
the
MOSFET bias point, the input resistance is then determined by the
bootstrap
resistor connecting the MOSFET gate to the collector/pullup resistor.
The
source current sensing resistor should be adequately decoupled and it
doesn't hurt to put a small capacitor to smooth the collector.

The MOSFET has higher input capacitance than the JFET but it also has
much
higher gain, you can cancel most of the capacitance by inserting a
degenerative feedback resistor between the current sense resistor and
source, this sacrifices gain and you set this to more like what you'd
expect
from a JFET.


Well, as far as Vdd headroom goes it's not so much the spread as Vgs
max and I'm not sure you're much, if any, better off selecting a
MOSFET than a jFET.

Well I suppose if you used a high voltage MOSFET from a SMPSU that had a
Vgs-thr in the direction of 6 - 8V it might get a bit tricky, might not do
too well at the frequency range suggested by the inductances in the OPs
design either.


The 2N5484 has a max pinch off of -3V, the BF245A is -2.2V max, and
the BF861A is -1V max.

Which MOSFET were you suggesting?

There's quite a few with Vgs-thr around 1V.

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

Hi Dave,
I just want to give a reminder about the Dallas files.
They have been moved and are being added to
a yahoo forum.
http://groups.yahoo.com/group/thedallasfiles/
He has not got all the files updated on the forum but
some are there.

Here's a High Z preamp with adjustments to improve IIP2.
I don't think this fills your need. but it shows his FET biasing.
Keep watching, he had a lot of amps for MW and SW on the other site.
I hope he posts all the previous files.
http://f1.grp.yahoofs.com/v1/cJXZTRF...mization. pdf
Mikek

"amdx" wrote in message
...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT (configured
for Common Emitter) to do this, but I am in the dark as to how this might
be accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

Hi Dave,
I just want to give a reminder about the Dallas files.
They have been moved and are being added to
a yahoo forum.
http://groups.yahoo.com/group/thedallasfiles/
He has not got all the files updated on the forum but
some are there.

Here's a High Z preamp with adjustments to improve IIP2.
I don't think this fills your need. but it shows his FET biasing.
Keep watching, he had a lot of amps for MW and SW on the other site.
I hope he posts all the previous files.
http://f1.grp.yahoofs.com/v1/cJXZTRF...mization. pdf
Mikek


Hey Mike, THANK YOU! Good to see you. Will definitely check that out.

Take it easy...

Dave

"amdx" wrote in message
...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT (configured
for Common Emitter) to do this, but I am in the dark as to how this might
be accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

Hi Dave,
I just want to give a reminder about the Dallas files.
They have been moved and are being added to
a yahoo forum.
http://groups.yahoo.com/group/thedallasfiles/
He has not got all the files updated on the forum but
some are there.

Here's a High Z preamp with adjustments to improve IIP2.
I don't think this fills your need. but it shows his FET biasing.
Keep watching, he had a lot of amps for MW and SW on the other site.
I hope he posts all the previous files.
http://f1.grp.yahoofs.com/v1/cJXZTRF...mization. pdf
Mikek


Hey Mike, just wanted to mention that this last link appears to be broken
(the one for the High Z preamp). Just thought you'd want to know...

Dave

"Dave" wrote in message
...


"amdx" wrote in message
...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT (configured
for Common Emitter) to do this, but I am in the dark as to how this might
be accomplished. ANY help would be greatly appreciated...

Thanks,

Dave

Hi Dave,
I just want to give a reminder about the Dallas files.
They have been moved and are being added to
a yahoo forum.
http://groups.yahoo.com/group/thedallasfiles/
He has not got all the files updated on the forum but
some are there.

Here's a High Z preamp with adjustments to improve IIP2.
I don't think this fills your need. but it shows his FET biasing.
Keep watching, he had a lot of amps for MW and SW on the other site.
I hope he posts all the previous files.
http://f1.grp.yahoofs.com/v1/cJXZTRF...mization. pdf
Mikek


Hey Mike, just wanted to mention that this last link appears to be broken
(the one for the High Z preamp). Just thought you'd want to know...

Dave
Sorry, start here, signup and go to files and then amplifiers.
http://groups.yahoo.com/group/thedallasfiles/
Mikek

"amdx" wrote in message
...


"Dave" wrote in message
...


"amdx" wrote in message
...

"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the following BJTs while keeping Vgs very near Pinch-Off. Works fine as
long as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold it at 3.95 VDC.) It has been suggested that I use a BJT
(configured for Common Emitter) to do this, but I am in the dark as to
how this might be accomplished. ANY help would be greatly
appreciated...

Thanks,

Dave

Hi Dave,
I just want to give a reminder about the Dallas files.
They have been moved and are being added to
a yahoo forum.
http://groups.yahoo.com/group/thedallasfiles/
He has not got all the files updated on the forum but
some are there.

Here's a High Z preamp with adjustments to improve IIP2.
I don't think this fills your need. but it shows his FET biasing.
Keep watching, he had a lot of amps for MW and SW on the other site.
I hope he posts all the previous files.
http://f1.grp.yahoofs.com/v1/cJXZTRF...mization. pdf
Mikek


Hey Mike, just wanted to mention that this last link appears to be broken
(the one for the High Z preamp). Just thought you'd want to know...

Dave
Sorry, start here, signup and go to files and then amplifiers.
http://groups.yahoo.com/group/thedallasfiles/
Mikek

Gotcha. Thanks.

It's only a stupid question if you already know the answer. Many
students have failed classes because they didn't ask what they thought
was a stupid question.





On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:


"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to the
following BJTs while keeping Vgs very near Pinch-Off. Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to hold
it at 3.95 VDC.) It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...

Thanks,

Dave




Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now all
my varactors are blown and I may have damaged one or more transistors. Will
be back later after I have sorted all this out.

JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows.
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.

Thanks.

Dave