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"flipper" wrote in message
...
On Thu, 19 May 2011 18:14:09 -0500, "Dave" wrote:
Once you get it repaired reconsider the original problem statement
"Dave" wrote in message
news
Am trying to bias the JFET in the attached schematic to feed signal to
the
following BJTs while keeping Vgs very near Pinch-Off.
Why are you trying to keep it near pinch off? At any rate, your
circuit wont'. It can't. You're biasing the gate and the jFET source
will settle at whatever Vgs produces a counter acting current, hence
source voltage, through the source resistor. That's why it sits at
9.6V.
Works fine as long
as the batteries are fresh, but as they begin to wane Vgs surpasses
Pinch-Off (which is 4.0 volts for the JFET I am using, while I try to
hold
it at 3.95 VDC.)
I don't know what symptom you're seeing but it shouldn't be the jFET
going into pinch off because the source voltage will simply change to
keep current flowing. You can't 'pinch it off' from gate bias because
it takes 4V (assuming that's Vgs pinch off) to do it, which means
there'd have to be at least 4V across the 3.2k, for 1.25mA (which is
clearly not pinched off), even if gate bias were 0. It clearly takes
even more current with gate positive and to pinch it off by the gate
you'd need a negative voltage source.
The jFET bias will fail when Vcc drops too low for the source voltage
to be generated, which would be around 7.5V, not from pinch off but
saturation. The signal will be clipped before that.
To explain (ignoring L4 DCR, jFET Rdson for simplicity), at 7.5V Vcc
the gate bias would be 3.525V and it takes 4 more volts (Vgs) on the
source, or 7.525V, for things to balance out but 7.525V cannot be
achieved with Vcc at 7.5V. So the jFET is biased 'full on', saturated,
trying to draw enough current to bring the source up to a voltage it
cannot get to.
It has been suggested that I use a BJT (configured for
Common Emitter) to do this, but I am in the dark as to how this might be
accomplished. ANY help would be greatly appreciated...
Thanks,
Dave
Okay, Murphy's Law rules. Was effecting a minor change in the biasing of
the JFET and when I hooked it all back up I let +12VDC hit the varactor D4
out of utter carelessness and too much wire where it wasn't needed. Now
all
my varactors are blown and I may have damaged one or more transistors.
Will
be back later after I have sorted all this out.
JT: Thanks for the input on the source resistor, but the NTE451 apparently
limits Id to 3mA by itself (much to my frustration). I don't need to do
that for it. What I do have to do is work with the 3mA it allows. 
It's your circuit that sets Ids and, as drawn, you have, at DC, a
crude constant current source set by (Vg+Vgs)/3200.
One problem with jFETs is the wide variation in Vgs makes them
difficult to bias with simple resistor networks. For example, Vgs on
that NTE451 ranges from .5V to 4V so if you swap in another one it
might end up drawing 1.9mA (which is a much smaller variation than the
8 to 1 Vgs range due to the crude 'current regulation' of the
degenerative 3200 Ohm resistor).
You could increase Vg to get more current, but that makes the 'low'
Vcc problem worse. Or you could lower the 3200 Ohm resistor but that
makes 'current regulation' worse.
A CCS under the source solves a number of sins by automatically
setting Vs at whatever it takes to cause that current to flow, with
the caveat Vg+Vgs(min) has to be high enough to cover the minimum
voltage drop across the type of CCS you use. A BJT current mirror is
good for that since they can operate down to Vce(sat) but I think a
degenerative emitter resistor is a good idea, especially for discrete
versions.
The current source JT posted is the same as I was thinking but,
considering the 'low Vcc' problem, you should probably lower your gate
bias voltage... and the emitter resistor a corresponding amount (more
if you want to increase Ids).
Anyway, I appreciate your input and may be back later if what I was trying
doesn't work to my satisfaction.
Thanks.
Dave
Man, thank you for the huge amount of input to process and digest. I'm
printing this to take back to my workshop for referrence, and so I don't
have to rely on my memory as to what all you said. One thing- please
correct me if I'm wrong, but I thought that pinch-off was when Vgs exceeded
minus 4VDC (for this JFET). And that was determined by subtracting Vg from
Vs (think I have that right.) Is this not correct?
Thanks again for the helpfull reply. I am honestly learning this as I go
along and don't mean to simply waste your time. Oh, and I was trying to
bias near pinch-off because I thought that this provided greater
amplification of the signal. Now I look at it and suspect that this is not
the case. That is why I was attempting to modify the bias on the JFET when
I blew the varactors.
Take it easy...
Dave
Dave