Posted to sci.electronics.design,alt.binaries.schematics.electronic,sci.electronics.cad
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Logic Question
"Jim Thompson" wrote in
message ...
On Thu, 10 Mar 2011 22:32:55 +0100, "Arie de Muynck"
wrote:
snip
You missed the part where what I really need is two circuits, each
with input A, but one with output A and the other with output Abar,
delay to each output EQUAL.
snip
Could you possibly add a buffer in order to create a 3 stage delay?
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