"Tom Del Rosso" wrote in message
...

Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity
generator (don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.

Maybe he just did not read this part of the thread. Or I'm blacklisted.
The beautiful symmetry should appeal to him.

And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't
it be driven high and low? (IANAEE)

No, hard driving one input high, the other low would overdrive conducting
B-E junctions.
And you need to pull the E's low hard to get the output at a logic low
level.
The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x
NPN):

|\ VCC
A --| -+------- E C -----+ |
|/ | B | (R)
\ /--(R)--+ | |
X +------+--- OUT
/ \--(R)--+ |
|\ | B |
B --| -+------- E C -----+
|/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie