Arie de Muynck wrote:
"Arie de Muynck" wrote:
I do remember it. I saw it inside a TTL EXOR circuit, maybe the
7486. Two NPN's, E and B cross connected to open collector drivers
(A and B), output taken from connected collectors, with a pull-up.
At least it is symmetrical, but maybe not too fast.


A ---- E1 -- B2 pull-up
|
C1 -- C2 --+--- OUT

B ---- B1 -- E2

I was thinking of the same thing, but it was the TTL 8-bit parity generator
(don't remember the number), not the 7486. I think the parity
generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked
this.


And of course it needed some pull-ups on the O.C. drivers as well...

If it was driven by another like it, as in the parity tree. But couldn't it
be driven high and low? (IANAEE)


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