Thread: Logic Question
View Single Post
  #22   Report Post  
Posted to sci.electronics.design,alt.binaries.schematics.electronic,sci.electronics.cad
Vladimir Vassilevsky[_2_] Vladimir Vassilevsky[_2_] is offline
external usenet poster
 
Posts: 27
Default Logic Question


Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?




m II wrote:
That is a simple OR gate. He wants an XOR gate.

-----------------
"Vladimir Vassilevsky" wrote in message
...
How about something like this:

http://www.abvolt.com/misc/xor.jpg


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com