On Tue, 08 Mar 2011 10:30:56 -0700, Jim Thompson wrote:

On Tue, 08 Mar 2011 11:22:52 -0600, Joe Chisolm
wrote:

On Mon, 07 Mar 2011 12:20:13 -0700, Jim Thompson wrote:

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

Never rolled my own at the device level but can you drive A through a
tristate inverter and a tristate buffer and then use B to select the
output?

I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat
equalize delay paths.

...Jim Thompson

Since you are rolling your own start with a 7474 D flop with /pre
and /clr. That would give you your Q and /Q. Strip out the clk gates
and just drive the /pre and /clr. The old data sheet for the SN7474
is still on the TI web site with the TTL schematic. The newer parts
like the 74ahc74 have logic diagrams. What is your A-out timing budget?




--
Joe Chisolm
Marble Falls, Tx.