"Jim Thompson" wrote in message
...

An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
-------------------

I am not sure where you get the uneven propagation delays.
Perhaps you are considering both logic levels switching at one time? I would
assume the logic inversion control input would already be quiescent.

(thinking out loud here)
Exclusive OR gates are quite simple complex gates (confusion intended)


Simply English text stated A or B but not both.

This equates to three simple gates

an OR gate = A+B 'this is the OR part, obviously
an NAND gate = NOT(A*B) 'this is the not both part
and one to combine the logic on the output 'this is what combines the two
conditions
AND = (A+B) * (NOT(A*B)

Now when A input is true (overall inversion) the A+B gate becomes blocked
at the output AND gate when B goes true.
Yup, the active NAND input gate NOT(A*B) has an extra inversion stage to
control the O/P AND gate.

When A input is false (no overall inversion) the A+B gate predominates at
the output of the AND gate when B goes true.
The inactive NAND input gate NOT(A*B) is not functioning in the output
signal through the O/P AND gate.

The same number of simple gates are used each logic but the transistor
stages are the same.

Perhaps slip a simple buffer into the output of the input OR gate to
increase it's propagation. Now you would have to find one with the same
number of stages as the NAND has for inversion hmmmm... not likely.

What type of logic family are you attempting to do this with? Logic insides
need to be known for this one.

Spec sheets are needed to spec propagation delay.


mike