Thread: Core Memory
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Tim Williams Tim Williams is offline
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Default Core Memory

"flipper" wrote in message
...
Well, as it turned out, the 'store' code with that relative addressing
mode was '0' and if the offset was '0' and you had '0' in the register
then it stored 0 in the next location and then executed that 0, which
did the same thing, storing another 0 in the next location, which it
then executed, which....

It simply zipped as fast as it could go perpetually writing zeroes
through all of memory over and over till you hit HALT. Mystery solved.


Yuck. It's pretty common to set 00000000b as NOP. In fact, I took
advantage of this the first time I ever got out a Z80-CPU to play with: I
wired it as an extremely inefficient 16-bit counter. Control lines pulled
up, D0-D7 = 00h, address lines open, LED on A15 to indicate operation.

Incidentially, I did a lot of playing with that thing without the luxury
of an oscilloscope or logic analyzer (being in my dorm room at the time).
That might be troublesome, but I just hooked a wire from breadboard to my
audio mixer and listened.

Loops buzz or whine. Multilevel loops buzz and click. Data processing
has a variety of multimode sounds, resembling FM synth with squarewaves
depending on what's being done. I wrote a 32 bit LFSR, which is indeed a
very effective source of white noise. I also wrote a tone generator,
which made something more harmonious than bus noises.

Speaking of which, I took the same tone generator code, ported it to the
AVR, and loaded the same data file:
http://myweb.msoe.edu/williamstm/Solfeg_Fast.mp3
Oops...... Z80 ran at 4MHz, AVR at 8 ;-)

Tim

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