flipper wrote:
On Thu, 12 Aug 2010 11:56:44 -0500, Dan wrote:

ian field wrote:
"flipper" wrote in message
...
On Thu, 12 Aug 2010 00:49:12 -0500, Dan wrote:

I have this core memory brick for which I want to find a good home.
I have no idea what it came out of. I have had it for 40 years and doubt
I ever knew.

Dan, U.S. Air Force, retired
Oh my, that is an oldie.

The core memory I've got is planar on a PCB.

The one I have/had is/was a PCB a bit more than a foot square with thousands
of tiny ferrite rings suspended by a matrix of wires and a third wire that
zig-zagged through every core.

It either got shoved behind the book shelf in the beddroom or slung out - I
can't remember which.


It should be 4 wires through each core. One each X and Y, and two
the zig zag through them all. One of the latter is sense, the other is
write.

Probably more than one way to skin a cat but, if memory serves (notice
the clever pun) the two zig zags were typically "sense" (as you
mentioned) and "inhibit".

The idea being, to speed things up, the planes were, conceptually,
'stacked' with multiple planes driven by the same X-Y select (each
inducing 1/2H) and then one, or more, of the planes in the 'stack'
could be 'inhibited' (I.E. remain '0') as the Z (inhibit) line (1/2H)
opposed the X-Y induction.

In modern parlance, translated to the 'stacked planes' arrangement,
that would be 'byte wise' vertical (assuming 8 planes). X-Y is 'byte
select' and Z (inhibit) selects the 'bit'.

I suppose one could consider that a 'write' line (inverted) but I
always heard it called inhibit (which initially confused the hell out
of me) and, technically, they're all involved in 'write' since it
takes the coincidence of all three, in the proper polarity, to induce
the magnetic field.

You then get a pulse on the (per plane) sense (bit) line if the core
(magnetization) flips.

Note that the data is non-volatile but read is destructive so the data
just read has to be rewritten.

They did make 3 wire planes too, though, with the one zig zag acting
as sense during read and inhibit during write but I don't know why
that wasn't done from the get go. Maybe it was easier, at the time, to
string a 2n'd ziggie than deal with isolating a low impedance driver
from the sense amp input.

They also made core 'PROMS', of a sort, called rope or braided wire
memory. You have a core for each bit and then 'factory program' which
are to be 1 or 0 by threading the select lines either through, or not
through, the corresponding bit core. If it goes through the bit core a
1 on that sense line will occur when selected and if it doesn't then
it won't. The data was 'wired in'.

For some reason I remembered it as write. I haven't played with with
the stuff since Pontius was a pilot. I don't recall 3 wire systems, but
I'll take your word.

I had forgotten rope memory until I saw a recent show on the Apollo
program where they were driving the women who made the ropes almost
crazy with rewrites. And to think I found machine code tedious.


Dan, U.S. Air Force, retired