On 2009-02-18, Jim Thompson wrote:

On 18 Feb 2009 11:22:03 GMT, Jasen Betts wrote:

On 2009-02-15, bw wrote:

"Jim Thompson" wrote in
message ...
Anyone used a 74HC191 UP/DOWN Counter, 3-stages?

Is there a way I can limit Terminal Count to 10-Bit?

can't you just ignore the two high bits ? or do the top two bits some
other way?


I need to simulate what another designer will ultimately do at
device-level. Counter must not over-run, top or bottom. (It's a
tracking ADC.)

I have it cobbled together and running with existing digital
(behavioral) parts in PSpice; so I can test my analog portions
quickly.

ah, I suppose you've already thought of this:

TC0 ---------------------------+- ___
TC1 ---------------------------|&)-- CE0
.---+-
bit8 --+------+- |
bit9 +-|------|&)---. |
| | .-o-+- | |
_ | | | `--+ |
U/D -|-|-+----+ )1-'
| `------)1o-----+
`--------+

TC0 and TC1 are TC from the low order chips ___
bit8,9 are D0 & D1 fron the high chip, and CE0
is clock enable on the low chip.


or could you just clock it 4 times faster and ignore the low bits?___
then you'd just need to and the three TCs together and feed it to CE0