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bz bz is offline
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Default CMOS DRAM chips and static

Paul wrote in
:

First, there are a lot of differences between pink antistatic bags!
they vary a lot in terms of what they are meant for, some are just for
NON-ESD sensitive components, and many are meant as ESD dissipative
bags.


Read this page
http://www.polypluspackaging.co.uk/a...s-material.php
It discusses which kind of bags you should use for different
applications. Notice that the low resistance ones are used for
shielding (Faraday cage), and the pink ones (dissipative - hi R) are
used to transport semiconductors.


The best bags to use are apparently the moisture resistant ones that have
an anti static [moderate conductive layer to avoid attracting sparks], a
highly conductive layer [Faraday shielding and good anti EMP shielding],
another other anti static layer [again to avoid sparking] and are heat
sealable and moisture proof. Pink bags are almost useless as are black bags
as they do not protect the contents from high voltage impulses near the
bag.


Nothing in ANY document I have seen so far says anything about a hazard due
to shorting the leads of an IC TOGETHER.

There is mention of discharging an INDUCED charge, via a leg during some of
the testing. The charge being induced in the assembly equipment by the
motion of the chips through the storage and assembly equipment.

One of the surprising 'reminders' [I should have remembered it from
physics] is that simply separating two conductors physically can induce a
charge. In other words, picking up a chip that has been laying on a
conductor or an insulator and lifting it vertically away from that surface
can create an electrical potential between the two objects unless they both
are grounded to a common point.

Thanks again for the interesting references.




--
bz

please pardon my infinite ignorance, the set-of-things-I-do-not-know is an
infinite set.

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