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bz bz is offline
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Default CMOS DRAM chips and static

Eeyore wrote in
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bz wrote:

Eeyore wrote

Aluminium foil is a BAD idea. In the event that there is any
appreciable charge on a given pin, pushing it into aluminium foil
will discharge it *quickly* and the resulting current may kill it.


It is NOT the current that kills CMOS, it is high VOLTAGE that punches
holes in the insulating layers inside the chip. [I am not aware of ANY
chip families where tiny CURRENTS would be a hazard].


These are two different things.


Yes.

Those 'tiny' currents can be quite large
when discharging a significant charge.


Yes, but you can not 'have a significant charge' on a chip without having
a high voltage differential between the chip and the conductor! There are
not enough charge carriers to produce a high current from the small
internal capacitances of the cmos chip itself. If you have enough of a
differential between leads on the chip to cause a high current, then you
have already lost the chip due to the high voltage.

Enought to damage the chip's
internals through overcurrent.


NO! The danger to cmos from static electricity is not due to over-current,
it is due to high voltage differential between high impedance gates and
the base substrate of the cmos chip.

The voltage punches a hole in the insulating oxide layer.

TTL chips and the gated devices in ICs can be damaged by excess current
but that current is from a current source, not the kind of small static
charge that is developed when you carelessly handle a cmos chip.

The use of aluminum foil for storage of static sensitive components is
safe because there can not be an 'appreciable charge' on a given pin
without the device already having been destroyed by the voltage!

Do some calculations and see what kinds of voltage one would need to
produce enough coulombs of charge carriers to produce damage from
excessive current on any IC. Remember, you have only the volume of the
metal conductors involved to hold those charges.

Envision a capacitor, fully charged (the floating gate). Charge it to the
MAXIMUM voltage that it can stand. Now throw a DEAD SHORT across the leads
that feed that capacitor and look at the current flow as the cap
discharges.

Compare that current with the normal charge/discharge currents that flow
as pulses drive the gate when the IC is mounted and being used normally.
Look at the rise and fall times. Look at the conductor materials used on
the chip and connecting the chip to the lead. Find the weakest point along
the current path and compute the maximum peak current that can flow in
that conductor and for how long that current can flow before it causes
damage. [remember, current causes damage by heat.]

Now, check to see if the max permissible voltage could possibly produce
that current.

I think you will find that even chips that have built in weak conductors
['fuses' designed to be burned open by current flow] could not possibly be
damaged by the small charge allowable between any two pins of a CMOS
device.

Now, there MIGHT be some conditions where metal foil would NOT be a good
idea, like those where electrolysis could develop, but we are not
discussing those.

Another condition would be where there are high intensity ELECTRIC fields
nearby, STRONG Pulsed magnetic fields or RF fields nearby. [such as EMP]
But then the chip would be destroyed even if it were soldered into a
circuit.

I have worked with components that are VERY static sensitive (point
contact detector diodes used in radars) that were ALSO easy to damage with
excessive current.

We sometimes had RF fields around that could cause excessive current flow.
We kept the diodes wrapped in foil until we were installing them.

There are times when EM shielded rooms, anti-static mats and wrist straps
are not available. When they are not available, I work on a sheet of
aluminum foil and make sure I touch the foil and the component before the
component touches the foil.

--
bz

please pardon my infinite ignorance, the set-of-things-I-do-not-know is an
infinite set.

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