Joel Koltner wrote:
These are some 'scope shots of a slightly misbehaving buck converter whereby
the duty cycle of the switch jitters around a bit when the input voltage is
~3V but doesn't do so at somewhat lower and higher voltages. (Output voltage
is 1.2V and maximum intended output current is around 150mA; the scope shots
were taken with a 20 ohm -- 60mA -- load connected. J6 and J7 are unjumpered
and R3 and C1 really are DNIed.)
I'm all ears for suggestions on how to improve this design, both the schematic
part and the layout. The layout is done with the idea that the four clustered
vias are the honest-to-God "ground" reference and that the controller's ground
and passive components' grounds don't see switching currents as much as
possible.
God fixes a lot of things but AFAICT not ground structures :-)
I am not a fan of clustered grounds but tend to use full ground planes
instead. Clever placement to avoid heavy currents from running right
across the chip area is still necessary but I think you did a pretty
good job there.
Things I've tried that didn't have a significant effect on the jitter:
-- Dropping 100nF from pin 5 to ground.
It would need a low ESR small cap there. I'd never run a switcher
without some kind of ceramic cap at the output.
-- Increasing C3, up to at least 1nF. Actually, the design doesn't even seem
to need C3 -- I'm thinking it's there to improve the high-frequency response
of the regulator? Linear's datasheet uses a 20pF cap (with a resistor ~5x
larger) in all their examples.
Even 100pF seems a bit high.
-- Dropping 100nF from the R4/R5 junction to ground.
That can make it go ballistic ;-)
-- Changed both the input and output capacitors (C4/C5) to 10uF ceramics.
Good idea. It also needs something ceramic to "lean on" for the input.
-- Raised C2 up to at least 1nF, which seriously cuts the loop bandwidth.
From doing some load step tests, down to about 2.8V the system is pretty
nicely damped and remains so at higher voltages; below 2.8V you do start to
see a handful of recovery cycles in the step response, but everything remains
stable. Dropping C2 to 100pF will make the loop unstable at voltage under
~3V.
-- Varied L1 anywhere from ~7.5uH to ~30uH. The size used -- 15uH -- is
larger than typically used, but was chosen based on staying in continuous
conduction mode down to a 20mA load with a 4.2V input.
I very much appreciate the time that people spend looking at stuff like this
on Usenet and thank you all for doing so!
A few comments:
R2 is high. If the worst case leakage of 1uA happens that would put you
above the min threshold.
You need a full ground plane. For example, the ground trace to R2
tunnels right through the "hot zone" underneath the inductor. As Mark
suggested run a big fat wire from the ground at R5 to pin 4 and another
from C2 to pin 4. Cut the ground trace to R2 off right at that resistor
and run a fat wire to pin 4. It'll be messy but this gets you as close
to a good ground as possible without a relayout.
Check the source. Does it become soft at the point where jitter starts?
I am sure you did this but just in case: Make sure your digital scope
definitely does not go into equivalent time sampling. Or just use a real
scope like a Tek 2465.
--
Regards, Joerg
http://www.analogconsultants.com/