Joel Koltner wrote:
(snip)
I'm all ears for suggestions on how to improve this design, both the schematic
part and the layout. The layout is done with the idea that the four clustered
vias are the honest-to-God "ground" reference and that the controller's ground
and passive components' grounds don't see switching currents as much as
possible.
(snip)

Layout:

The trace necks down very thin at U1, pin 6. Why?

Must there be clear space under the chip? If not, why not
broaden Vbat and Gnd under it to reduce the inductance back
to C4?

Opposite comment for U1 pin 5 to L1. This node should have
the absolute lowest capacitance to everything, so the pad
sizes should be just what is needed for soldering and the
trance width just what the current needs. No square corners
if a diagonal will do.

I would try to add a small ceramic chip cap to ground
between L1 and everything else connected to the Vout node,
with the smallest loop area back to the ground side of C4
and U1 pin 4. That ground return path can be a separate
trace from the ground fill, to keep that high frequency
current through L1's parallel capacitance out of the ground
system.




--
Regards,

John Popelish