flipper wrote:
On Fri, 18 Jan 2008 13:15:10 -0800, Joerg
wrote:

flipper wrote:
On Fri, 18 Jan 2008 11:02:52 -0800, Joerg
wrote:

robb wrote:
"Joerg" wrote in message
. ..
robb wrote:
"John Popelish" wrote in message
. ..
robb wrote
This is the my 1st SMT pcb etching project board.
Is there anything horribly wrong with the layout of the
components and/or traces ?

I am also concerned that it looks like you have loaded the
output of one of the opamps directly with capacitors, which
tends to make them oscillate. And one opamp looks dangling.
Usually a bad idea. Maybe we should look at the
schematic, also.

Why are R9 through 12 arranges as they are
Regards,John Popelish

I have made some modifications and i have added a schematic
image
along with the pcb,

Hmm, first reply went into the weeds.

Still no bypass cap close by. This is not a super-fast opamp
but it is
isn't slow enough to go sans cap. C1/C2 are a bit far away.
Also,
driving the center of C1/C2 directly can cause some grief. Most
opamps
do not like to have a large capacitive load and may oscillate.

Hint: To make your circuits more understandable draw them with
the
individual opamp sections separated, not all in one big block.
Else
you'll sit there a few years later "What on earth does this
part here do?"
Pins 1 and 2 are connected in the layout but not on the
schematic ...
--
Regards, Joerg
http://www.analogconsultants.com/
Thanks for help Joerg,
The replies do not go to weeds, i am just a hobby/amateur, slow
and methodic. Plus going from 2 cm spacing to 1cm seems pretty
close to me ? also i did not realize that 1 uF was a considered
a large capacitive load.

The design of the circuit is not mine (obvious yes) i simply
re-drew a schematic i found on the web using a schematic tool so
that it would be easier to make the PCB layout using the
schematic software's NET tool that shows what components are
connected when you click their pads. I just select the components
from the component manager. IC1 is a standard Quad OPAMP from the
schematic app's component library.

So the original schematic i am using for my SMT/etch project is
here

http://www.qsl.net/iz7ath/web/02_bre..._esr/fig03.gif

when i want to fiure out what it does i can look at my print out
of the original

thanks again for the help and ideas,
robb

Massa fittizia sounds so much nicer than virtual ground but that load on
IC1A definitely does not look ok. Figure 15 shows how to do it right:

http://www.ee.unb.ca/Courses/EE3122/...plications.pdf
IC1A is already at unity gain.

That doesn't necessarily guarantee that it won't misbehave with such a
massive capacitive load. I would not do it.

I understand how you feel, and it makes me nervous too, but the point
was that circuit example isn't applicable. There's no gain to roll off
and the best C1 could do is bring gain down to what it already is.


Well, I have seen amps that were unity gain stable go into a tarantella
dance when presented with a big enough capacitive load.


Strikes me that huge caps on the output is the wrong place to
'filter'. What I usually see for virtual ground is filter the input
power and take it (VG) directly from the opamp with, perhaps, a
current limiting/capacitive load stability series resistor (in the
loop) and a few puffs for noise/stability.


A big cap across the output can also be a sure-fire method to fry the
output section of the opamp upon connection of a nice fresh battery.
Phssst ... pop ... poof.

--
Regards, Joerg

http://www.analogconsultants.com/