Joerg wrote:
John Popelish wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is
100K. I mean, that shouldn't be any load to write home about even for
a CD series part.


I understand that you have no more room for inverter packs, but could
you jam in a few more resistors or capacitors? If so, you could
improve the feedback system to pass through the 1/2 Vdd threshold a
lot faster for the same frequency, and, thus, narrow the high current
ramps.

From your scope pictures, I am assuming that the timing capacitor is
about 30 nF. If so, this configuration should give you about the
same frequency, but at a fraction of the average shoot through current
for 2 extra passives:


|\ |\
+--| O---+--------| O-+
| |/ | |/ |
| .-. |
| | |20k |
| | | |
.-. '-' |
| | | || 100n |
| | 500k +----||--+ |
'-' | || | |
| .-. === |
| | | GND |
| | | |
| '-'100k |
| | ||20n|
+---------+--------||---+
||

This configuration reduces the negative feedback and load on the
second inverter and steepens the approach to Vdd/2 at the input of the
first one.


Thanks. I wish I could do that but the layout, board fab and stuffing is
done :-(

Before we do a re-layout I will certainly look into this, or maybe throw
in my own transistor oscillator where I know I can get them under 10uA.
Another 40106 isn't an option because these sections must be independent
for safety reasons. While they did port the CD4000 to TSSOP it doesn't
come in singles.

You might also look at the variation where the feedback
capacitor is split into two capacitors in series to ground,
( a capacitive divider) each, half of the original
capacitance, and eliminate the 500k current limiting
capacitor to the first input. This puts a large capacitive
load on the second inverter, slowing its rise and fall time,
but actually lowers the second inverter's average supply
current by about a factor of 4, since only 1/4th the total
capacitance has to be charged up 10 volts and dumped each
cycle. But all that charge now has to be delivered during
the rise and fall time, instead of during the timing phase.
But it takes the clamp diodes out of the timing equation,
so that the oscillator is more temperature stable.

If you want to speed it up even a bit more, add a resistor
in series with the grounded capacitor of the output divider
that is about equal to the inverter output resistance.
This doesn't change the supply current consumed to charge
the divider, but speeds the transition of the first stage a
bit more. Whether that view is worth the climb depends on
how much faster that first stage is swinging.

Once this series of changes in implemented, the timing
waveform at the input if the first inverter can be made to
be an almost perfect ramp, instead of an exponential.
Constant rate of voltage change.