Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.

--
Regards, Joerg

http://www.analogconsultants.com

On Fri, 03 Aug 2007 22:20:53 GMT, Joerg
wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.

Joerg!!

Out1 looks normal to me. Think about it.

Out 2 looks like it's AC-coupled, or you're not looking where you
think.

Or maybe because it's not English ?:-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Joerg wrote:
Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.

There has to be some rate of change in the output voltage
before net positive feedback overtakes the negative
feedback around the second stage to flip the state. I think
what you see is pretty normal for this configuration.

Jim Thompson wrote:

On Fri, 03 Aug 2007 22:20:53 GMT, Joerg
wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


Joerg!!

Out1 looks normal to me. Think about it.


Normal? Well, maybe they put an inverter with really lousy gain in
there. In an RC oscillator that can cause lots of wasted power (which is
what I am seeing). Oh do I wish I had two more CD40106 inverter, but not
this time.


Out 2 looks like it's AC-coupled, or you're not looking where you
think.


The yellow trace is OUT2, the blue one is the left node of the cap. Both
DC-coupled.


Or maybe because it's not English ?:-)


Oops. Got to get into Margarita mode for tonight ;-)

--
Regards, Joerg

http://www.analogconsultants.com

John Popelish wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.


There has to be some rate of change in the output voltage before net
positive feedback overtakes the negative feedback around the second
stage to flip the state. I think what you see is pretty normal for this
configuration.


Yeah, probably a wimpy single stage inverter instead of the usual three.
Bottomline this thing now consumes around 100uA and more.

--
Regards, Joerg

http://www.analogconsultants.com

On Fri, 03 Aug 2007 15:46:32 -0700, Joerg
wrote:

Jim Thompson wrote:

On Fri, 03 Aug 2007 22:20:53 GMT, Joerg
wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


Joerg!!

Out1 looks normal to me. Think about it.


Normal? Well, maybe they put an inverter with really lousy gain in
there. In an RC oscillator that can cause lots of wasted power (which is
what I am seeing). Oh do I wish I had two more CD40106 inverter, but not
this time.


Out 2 looks like it's AC-coupled, or you're not looking where you
think.


The yellow trace is OUT2, the blue one is the left node of the cap. Both
DC-coupled.


Or maybe because it's not English ?:-)


Oops. Got to get into Margarita mode for tonight ;-)

Blue trace is normal, yellow trace indicates that OUT2 can't support
the current. Increase the resistance value.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

On Fri, 03 Aug 2007 22:20:53 +0000, Joerg wrote:

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.

Stupid question, but are your probes compensated? ;-)

It kind of looks like you don't have enough feedback - i.e. your resistors
are too high in resistance, or maybe your cap is too small.

Your plot is incomprehemsible, but I'd expect "OUT 1" to look like
your blue trace there.

Good Luck!
Rich

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin 9.

Do you think that the sag might be due to the input voltage approaching the
threshold, and the finite gain of the gate? I would expect this to be
especially likely if it is an unbuffered version.

Chris

Jim Thompson wrote:
On Fri, 03 Aug 2007 15:46:32 -0700, Joerg
wrote:


Jim Thompson wrote:


On Fri, 03 Aug 2007 22:20:53 GMT, Joerg
wrote:



Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


Joerg!!

Out1 looks normal to me. Think about it.


Normal? Well, maybe they put an inverter with really lousy gain in
there. In an RC oscillator that can cause lots of wasted power (which is
what I am seeing). Oh do I wish I had two more CD40106 inverter, but not
this time.



Out 2 looks like it's AC-coupled, or you're not looking where you
think.


The yellow trace is OUT2, the blue one is the left node of the cap. Both
DC-coupled.



Or maybe because it's not English ?:-)


Oops. Got to get into Margarita mode for tonight ;-)


Blue trace is normal, yellow trace indicates that OUT2 can't support
the current. Increase the resistance value.


Had to dip into the pool, it's 100F out here.

John's post got me thinking, it's probably a wimpy 1-stage inverter and
crossing over slowly. The sag is the same with 100K as it is with 33.2K
on the next timer.

I wonder why they didn't put a real inverter in there because this one
isn't part of the oscillator for crystal operation (that only uses the
first one).

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

Joerg wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin 9.


Nope, yellow is pin 9.


Do you think that the sag might be due to the input voltage approaching the
threshold, and the finite gain of the gate? I would expect this to be
especially likely if it is an unbuffered version.


Yes, it seems to be the case. Beats me why they placed an unbuffered
inverter there, doesn't make much sense to me. Maybe batteries were
cheaper in the 70's when these chips were born ;-)

--
Regards, Joerg

http://www.analogconsultants.com

Rich Grise wrote:

On Fri, 03 Aug 2007 22:20:53 +0000, Joerg wrote:

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


Stupid question, but are your probes compensated? ;-)


Yes, and the power cord is plugged in :-)


It kind of looks like you don't have enough feedback - i.e. your resistors
are too high in resistance, or maybe your cap is too small.


These chips are often used with smaller resistors and caps up to 20uF.


Your plot is incomprehemsible, but I'd expect "OUT 1" to look like
your blue trace there.


Hey, this is a brand new scope ....

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


Joerg wrote:



Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin
9.


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.


(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.

--
Regards, Joerg

http://www.analogconsultants.com

On Fri, 03 Aug 2007 17:12:14 -0700, Joerg
wrote:

Chris Jones wrote:

Joerg wrote:
[snip]

Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.


(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.

Now that you have the pins identified, do you have the components
connected correctly ?:-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Ok, Chris and Rich, you were right, I was indeed on pin 10.

So, I measured the supply current. Here is pin 10 (yellow) and the
supply current (blue). 100mV equals 100uA. The sag is indeed due to the
sluggish inverter and the thing peaks up to a whopping 400uA of cross
current. That is huge.

--
Regards, Joerg

http://www.analogconsultants.com

Jim Thompson wrote:

On Fri, 03 Aug 2007 17:12:14 -0700, Joerg
wrote:


Chris Jones wrote:


Joerg wrote:

[snip]

Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.



(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Now that you have the pins identified, do you have the components
connected correctly ?:-)


Yep :-)))

redness in the face slowly vanishes ...

Take a look at the pic in the other post. Is 400uA cross current peak
normal for CD4000 chips running around 10V? I've used unbuffered chips
in analog fashion before but they never began to cross conduct with the
input more than 2V away from center.

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


Joerg wrote:



Chris Jones wrote:



Joerg wrote:




Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on

both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin
9.


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.



(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Well, I don't see what you mean by sluggish - the edges are pretty crisp on
this timescale and the droop at the end of the yellow waveform can be
explained as follows:

You're looking at Out1, I think. So the blue is the input to an inverter
and the yellow is the output of the same inverter. The blue (input) is
very slowly approaching the threshold of the inverter and as the input gets
very close to the threshold, by definition, the output will also start to
approach the threshold.

Look at the other output, out2, and the droop should be gone.


I did, and it is gone. But I've not yet seen CD4000 unbuffered inverters
begin to cross conduct so far away from center. Then again I don't do
analog stuff with them at such high supplies.

--
Regards, Joerg

http://www.analogconsultants.com

On Sat, 04 Aug 2007 00:26:36 GMT, Joerg
wrote:

Ok, Chris and Rich, you were right, I was indeed on pin 10.

So, I measured the supply current. Here is pin 10 (yellow) and the
supply current (blue). 100mV equals 100uA. The sag is indeed due to the
sluggish inverter and the thing peaks up to a whopping 400uA of cross
current. That is huge.

I have versions of...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

without the attenuator ("no-clip"), since there's no ESD protection
needed inside a chip, that run at 2MHz, consuming 1uA ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

On Fri, 03 Aug 2007 17:32:53 -0700, Joerg
wrote:

Jim Thompson wrote:

On Fri, 03 Aug 2007 17:12:14 -0700, Joerg
wrote:


Chris Jones wrote:


Joerg wrote:

[snip]

Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.



(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Now that you have the pins identified, do you have the components
connected correctly ?:-)


Yep :-)))

redness in the face slowly vanishes ...

Take a look at the pic in the other post. Is 400uA cross current peak
normal for CD4000 chips running around 10V? I've used unbuffered chips
in analog fashion before but they never began to cross conduct with the
input more than 2V away from center.

How much is the scope probe capacitance consuming ?:-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

On Sat, 04 Aug 2007 00:26:36 GMT, Joerg
wrote:


Ok, Chris and Rich, you were right, I was indeed on pin 10.

So, I measured the supply current. Here is pin 10 (yellow) and the
supply current (blue). 100mV equals 100uA. The sag is indeed due to the
sluggish inverter and the thing peaks up to a whopping 400uA of cross
current. That is huge.


I have versions of...

http://analog-innovations.com/SED/CMOS-Osc-NoClip.pdf

without the attenuator ("no-clip"), since there's no ESD protection
needed inside a chip, that run at 2MHz, consuming 1uA ;-)


Nice. I usually do mine with a 40106. Not 1uA but under 10uA which would
be way sufficient here. However, I had to get about 60 parts onto the
area of a postage stamp and I didn't have any "good" inverters left over
anywhere. This 4060 oscillator sure is a disappointment.

--
Regards, Joerg

http://www.analogconsultants.com

Jim Thompson wrote:

On Fri, 03 Aug 2007 15:46:32 -0700, Joerg
wrote:

Jim Thompson wrote:

On Fri, 03 Aug 2007 22:20:53 GMT, Joerg
wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


Joerg!!

Out1 looks normal to me. Think about it.


Normal? Well, maybe they put an inverter with really lousy gain in
there. In an RC oscillator that can cause lots of wasted power (which is
what I am seeing). Oh do I wish I had two more CD40106 inverter, but not
this time.


Out 2 looks like it's AC-coupled, or you're not looking where you
think.


The yellow trace is OUT2, the blue one is the left node of the cap. Both
DC-coupled.


Or maybe because it's not English ?:-)


Oops. Got to get into Margarita mode for tonight ;-)

Blue trace is normal, yellow trace indicates that OUT2 can't support
the current. Increase the resistance value.

...Jim Thompson


If this were the case....
Out2 goes up suddenly (centre of graph) and blue trace perversely decides to
suddenly go down??? By what mechanism would it do that?

I think the yellow trace might be OUT1 = Pin 10.

Chris

Jim Thompson wrote:

On Fri, 03 Aug 2007 17:32:53 -0700, Joerg
wrote:


Jim Thompson wrote:


On Fri, 03 Aug 2007 17:12:14 -0700, Joerg
wrote:



Chris Jones wrote:



Joerg wrote:

[snip]


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.




(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Now that you have the pins identified, do you have the components
connected correctly ?:-)


Yep :-)))

redness in the face slowly vanishes ...

Take a look at the pic in the other post. Is 400uA cross current peak
normal for CD4000 chips running around 10V? I've used unbuffered chips
in analog fashion before but they never began to cross conduct with the
input more than 2V away from center.


How much is the scope probe capacitance consuming ?:-)


Hey, this is a brand new 200MHz scope that came with four spanking new
high speed probes :-D

Now I don't need to fumble with the digital camera anymore and no
wielding of GPIB garden hoses. Hook up scope, hit save, select LAN
drive, click ok. Go to newsgroup PC in office next door (the really old
Gerber viewing PC here), post to Usenet.

--
Regards, Joerg

http://www.analogconsultants.com

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


Joerg wrote:



Chris Jones wrote:



Joerg wrote:




Chris Jones wrote:




Joerg wrote:





Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is
100K. I mean, that shouldn't be any load to write home about even for
a CD series part.



From the polarity of the step in the waveform (which must be the same

on

both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not
Pin 9.


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.




(or are you sure the pin numbers on the schematic are right?) It
doesn't make sense if Out2 jumps up in the middle of the scope display
and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Well, I don't see what you mean by sluggish - the edges are pretty crisp
on this timescale and the droop at the end of the yellow waveform can be
explained as follows:

You're looking at Out1, I think. So the blue is the input to an inverter
and the yellow is the output of the same inverter. The blue (input) is
very slowly approaching the threshold of the inverter and as the input
gets very close to the threshold, by definition, the output will also
start to approach the threshold.

Look at the other output, out2, and the droop should be gone.


I did, and it is gone. But I've not yet seen CD4000 unbuffered inverters
begin to cross conduct so far away from center. Then again I don't do
analog stuff with them at such high supplies.



The relevant measure is "how far away from the nearest supply rail", not
"how close to the centre". If it is further from the VDD rail than the
p-channel threshold, and further from the VSS rail than the n-channel
threshold then you'll get plenty of supply current.


Sure, but I've never seen 400uA on a lone unbuffered inverter at 10V. At
15V, maybe, but even there it used to be lower.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:

Chris Jones wrote:

Joerg wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin
9.


Nope, yellow is pin 9.

Are you *sure* sure ?

(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.

Chris

Joerg wrote:

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


Joerg wrote:



Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin
9.


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.


(or are you sure the pin numbers on the schematic are right?) It doesn't
make sense if Out2 jumps up in the middle of the scope display and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.

Well, I don't see what you mean by sluggish - the edges are pretty crisp on
this timescale and the droop at the end of the yellow waveform can be
explained as follows:

You're looking at Out1, I think. So the blue is the input to an inverter
and the yellow is the output of the same inverter. The blue (input) is
very slowly approaching the threshold of the inverter and as the input gets
very close to the threshold, by definition, the output will also start to
approach the threshold.

Look at the other output, out2, and the droop should be gone.

Chris

Joerg wrote:

Chris Jones wrote:

Joerg wrote:


Chris Jones wrote:


Joerg wrote:



Chris Jones wrote:



Joerg wrote:




Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is
100K. I mean, that shouldn't be any load to write home about even for
a CD series part.



From the polarity of the step in the waveform (which must be the same
on

both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not
Pin 9.


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is pin
10. Still puzzled why the transition is so sluggish. At 8-10V I would
have expected a lot more oomph even from a single stage inverter.



(or are you sure the pin numbers on the schematic are right?) It
doesn't make sense if Out2 jumps up in the middle of the scope display
and the
other end of the cap jumps down. Since that doesn't make sense, I think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the old
HCU04 has more zing.


Well, I don't see what you mean by sluggish - the edges are pretty crisp
on this timescale and the droop at the end of the yellow waveform can be
explained as follows:

You're looking at Out1, I think. So the blue is the input to an inverter
and the yellow is the output of the same inverter. The blue (input) is
very slowly approaching the threshold of the inverter and as the input
gets very close to the threshold, by definition, the output will also
start to approach the threshold.

Look at the other output, out2, and the droop should be gone.


I did, and it is gone. But I've not yet seen CD4000 unbuffered inverters
begin to cross conduct so far away from center. Then again I don't do
analog stuff with them at such high supplies.


The relevant measure is "how far away from the nearest supply rail", not
"how close to the centre". If it is further from the VDD rail than the
p-channel threshold, and further from the VSS rail than the n-channel
threshold then you'll get plenty of supply current.

Chris

Joerg a écrit :
Jim Thompson wrote:

On Fri, 03 Aug 2007 17:32:53 -0700, Joerg
wrote:


Jim Thompson wrote:


On Fri, 03 Aug 2007 17:12:14 -0700, Joerg
wrote:



Chris Jones wrote:



Joerg wrote:

[snip]


Nope, yellow is pin 9.


Are you *sure* sure ?


Not so sure anymore. Used the wrong datasheet. You are right, it is
pin 10. Still puzzled why the transition is so sluggish. At 8-10V I
would have expected a lot more oomph even from a single stage
inverter.




(or are you sure the pin numbers on the schematic are right?) It
doesn't
make sense if Out2 jumps up in the middle of the scope display and
the
other end of the cap jumps down. Since that doesn't make sense, I
think
something is wrong here.


I guess so. How embarrassing. But why is it so sluggish? Even the
old HCU04 has more zing.


Now that you have the pins identified, do you have the components
connected correctly ?:-)


Yep :-)))

redness in the face slowly vanishes ...

Take a look at the pic in the other post. Is 400uA cross current peak
normal for CD4000 chips running around 10V? I've used unbuffered
chips in analog fashion before but they never began to cross conduct
with the input more than 2V away from center.


How much is the scope probe capacitance consuming ?:-)


Hey, this is a brand new 200MHz scope that came with four spanking new
high speed probes :-D


Joerg,
you probably already checked it but just in case...
I've bought some of the cheap chinease 1/1:10 scope probe for slow 1:1
probing. That's perfectly OK for that. Now, to once do a quick circuit
check I flipped it to the 1:10 mode and scratched my head for the bad
results of my circuit for maybe an hour...
.... until I noticed that the 1:10 attenuation was of by more than 20%.
Not AC response, but DC. What a crap!

Now I believe it's fortunate they got the 1:1 ratio right :-)


Now I don't need to fumble with the digital camera anymore and no
wielding of GPIB garden hoses. Hook up scope, hit save, select LAN
drive, click ok. Go to newsgroup PC in office next door (the really old
Gerber viewing PC here), post to Usenet.


With a PC running windo$e you wouldn't even have to cross the door :-)


--
Thanks,
Fred.

Fred_Bartoli wrote:


[...]

How much is the scope probe capacitance consuming ?:-)


Hey, this is a brand new 200MHz scope that came with four spanking new
high speed probes :-D


Joerg,
you probably already checked it but just in case...
I've bought some of the cheap chinease 1/1:10 scope probe for slow 1:1
probing. That's perfectly OK for that. Now, to once do a quick circuit
check I flipped it to the 1:10 mode and scratched my head for the bad
results of my circuit for maybe an hour...
... until I noticed that the 1:10 attenuation was of by more than 20%.
Not AC response, but DC. What a crap!

Now I believe it's fortunate they got the 1:1 ratio right :-)


When the scope came that's one of the first things I checked. Took the
fast pulse generator. To my amazement they had even adjusted the
compensation very close to perfect.

But for most of my jobs I need direct 50ohm coax or a FET probe.


Now I don't need to fumble with the digital camera anymore and no
wielding of GPIB garden hoses. Hook up scope, hit save, select LAN
drive, click ok. Go to newsgroup PC in office next door (the really
old Gerber viewing PC here), post to Usenet.


With a PC running windo$e you wouldn't even have to cross the door :-)


Yeah, I could subscribe to usenet from the PC in the lab. Even have the
threaded header files on the LAN drive so the read/unread status jibes
no matter which one I use. But as it is engineers sit too much. It takes
only a matter of seconds to dart over to the office but you must get out
of the chair which is a good thing. This is also why there is one of
those knee chairs in the lab without a back rest. Forces me to sit
straight, you can't slouch on those.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg a écrit :
Fred_Bartoli wrote:


[...]

How much is the scope probe capacitance consuming ?:-)


Hey, this is a brand new 200MHz scope that came with four spanking
new high speed probes :-D


Joerg,
you probably already checked it but just in case...
I've bought some of the cheap chinease 1/1:10 scope probe for slow 1:1
probing. That's perfectly OK for that. Now, to once do a quick circuit
check I flipped it to the 1:10 mode and scratched my head for the bad
results of my circuit for maybe an hour...
... until I noticed that the 1:10 attenuation was of by more than 20%.
Not AC response, but DC. What a crap!

Now I believe it's fortunate they got the 1:1 ratio right :-)


When the scope came that's one of the first things I checked. Took the
fast pulse generator. To my amazement they had even adjusted the
compensation very close to perfect.


Yep, pulse shape was OK too (for the price). But who would think of
testing DC attenutation? Now I do...

--
Thanks,
Fred.

Fred_Bartoli wrote:

Joerg a écrit :

Fred_Bartoli wrote:


[...]


How much is the scope probe capacitance consuming ?:-)


Hey, this is a brand new 200MHz scope that came with four spanking
new high speed probes :-D


Joerg,
you probably already checked it but just in case...
I've bought some of the cheap chinease 1/1:10 scope probe for slow
1:1 probing. That's perfectly OK for that. Now, to once do a quick
circuit check I flipped it to the 1:10 mode and scratched my head for
the bad results of my circuit for maybe an hour...
... until I noticed that the 1:10 attenuation was of by more than 20%.
Not AC response, but DC. What a crap!

Now I believe it's fortunate they got the 1:1 ratio right :-)


When the scope came that's one of the first things I checked. Took the
fast pulse generator. To my amazement they had even adjusted the
compensation very close to perfect.


Yep, pulse shape was OK too (for the price). But who would think of
testing DC attenutation? Now I do...


Hmm, should be almost an automatic habit. The manual of this scope
actually said so right in front and this was repeated on the cal sheet
in each probe pouch: Hook up probes to calibration point, adjust slope
and verify Vpp for both x1 and x10 settings. With a wrong DC level Vpp
would have to be wrong as well. And this is a Taiwanese scope, not from
one of the usual manufacturers. I bought it mostly because I absolutely
did not want to be stuck with the paltry 2.5K memory that Tektronix
offered. Now I've got ten times that.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.


------------------------------------------------------------------------


------------------------------------------------------------------------

It looks like normal behavior for the gaye oscillaotr! AS the feedback
signal apporahes the logis threshold, the front end of the logic gate
leaves the "digital" realm, where we only have cut off and saturation,
and enters......... the analog linear zone. so the out ut then has a
gain of about *;! for a slwly vaying input...till the thershaold is met,
the devcie swicthes.. the inout signal are largelry seprated
(magnitude...and you're back in the digital "realm".

Marc

I knw exactly how to sqaure this up too

Joerg wrote:
Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.

I understand that you have no more room for inverter packs,
but could you jam in a few more resistors or capacitors? If
so, you could improve the feedback system to pass through
the 1/2 Vdd threshold a lot faster for the same frequency,
and, thus, narrow the high current ramps.

From your scope pictures, I am assuming that the timing
capacitor is about 30 nF. If so, this configuration should
give you about the same frequency, but at a fraction of
the average shoot through current for 2 extra passives:


|\ |\
+--| O---+--------| O-+
| |/ | |/ |
| .-. |
| | |20k |
| | | |
.-. '-' |
| | | || 100n |
| | 500k +----||--+ |
'-' | || | |
| .-. === |
| | | GND |
| | | |
| '-'100k |
| | ||20n|
+---------+--------||---+
||

This configuration reduces the negative feedback and load on
the second inverter and steepens the approach to Vdd/2 at
the input of the first one.

LVMarc wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.


------------------------------------------------------------------------


------------------------------------------------------------------------

It looks like normal behavior for the gaye oscillaotr! AS the feedback
signal apporahes the logis threshold, the front end of the logic gate
leaves the "digital" realm, where we only have cut off and saturation,
and enters......... the analog linear zone. so the out ut then has a
gain of about *;! for a slwly vaying input...till the thershaold is met,
the devcie swicthes.. the inout signal are largelry seprated
(magnitude...and you're back in the digital "realm".

Marc

I knw exactly how to sqaure this up too




Well, it's squared up alright but the cross-current's net contribution
to the total battery consumption is painful.

--
Regards, Joerg

http://www.analogconsultants.com

John Popelish wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.


I understand that you have no more room for inverter packs, but could
you jam in a few more resistors or capacitors? If so, you could improve
the feedback system to pass through the 1/2 Vdd threshold a lot faster
for the same frequency, and, thus, narrow the high current ramps.

From your scope pictures, I am assuming that the timing capacitor is
about 30 nF. If so, this configuration should give you about the same
frequency, but at a fraction of the average shoot through current for 2
extra passives:


|\ |\
+--| O---+--------| O-+
| |/ | |/ |
| .-. |
| | |20k |
| | | |
.-. '-' |
| | | || 100n |
| | 500k +----||--+ |
'-' | || | |
| .-. === |
| | | GND |
| | | |
| '-'100k |
| | ||20n|
+---------+--------||---+
||

This configuration reduces the negative feedback and load on the second
inverter and steepens the approach to Vdd/2 at the input of the first one.


Thanks. I wish I could do that but the layout, board fab and stuffing is
done :-(

Before we do a re-layout I will certainly look into this, or maybe throw
in my own transistor oscillator where I know I can get them under 10uA.
Another 40106 isn't an option because these sections must be independent
for safety reasons. While they did port the CD4000 to TSSOP it doesn't
come in singles.

--
Regards, Joerg

http://www.analogconsultants.com

On Sat, 04 Aug 2007 13:05:08 -0700, Joerg
wrote:

LVMarc wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.


------------------------------------------------------------------------


------------------------------------------------------------------------

It looks like normal behavior for the gaye oscillaotr! AS the feedback
signal apporahes the logis threshold, the front end of the logic gate
leaves the "digital" realm, where we only have cut off and saturation,
and enters......... the analog linear zone. so the out ut then has a
gain of about *;! for a slwly vaying input...till the thershaold is met,
the devcie swicthes.. the inout signal are largelry seprated
(magnitude...and you're back in the digital "realm".

Marc

I knw exactly how to sqaure this up too




Well, it's squared up alright but the cross-current's net contribution
to the total battery consumption is painful.

That's why my 3-inverter version is so much better... speed-up thru
the threshold region.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

America: Land of the Free, Because of the Brave

Jim Thompson wrote:

On Sat, 04 Aug 2007 13:05:08 -0700, Joerg
wrote:


LVMarc wrote:


Joerg wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K.
I mean, that shouldn't be any load to write home about even for a CD
series part.


------------------------------------------------------------------------


------------------------------------------------------------------------


It looks like normal behavior for the gaye oscillaotr! AS the feedback
signal apporahes the logis threshold, the front end of the logic gate
leaves the "digital" realm, where we only have cut off and saturation,
and enters......... the analog linear zone. so the out ut then has a
gain of about *;! for a slwly vaying input...till the thershaold is met,
the devcie swicthes.. the inout signal are largelry seprated
(magnitude...and you're back in the digital "realm".

Marc

I knw exactly how to sqaure this up too




Well, it's squared up alright but the cross-current's net contribution
to the total battery consumption is painful.


That's why my 3-inverter version is so much better... speed-up thru
the threshold region.


Well, if Lansdale or someone else would offer all three inverters in a
newly invented SC-75-5 package for under 30c I could possibly squeeze it
in ;-)

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
John Popelish wrote:

Joerg wrote:

Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is
at pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is
100K. I mean, that shouldn't be any load to write home about even for
a CD series part.


I understand that you have no more room for inverter packs, but could
you jam in a few more resistors or capacitors? If so, you could
improve the feedback system to pass through the 1/2 Vdd threshold a
lot faster for the same frequency, and, thus, narrow the high current
ramps.

From your scope pictures, I am assuming that the timing capacitor is
about 30 nF. If so, this configuration should give you about the
same frequency, but at a fraction of the average shoot through current
for 2 extra passives:


|\ |\
+--| O---+--------| O-+
| |/ | |/ |
| .-. |
| | |20k |
| | | |
.-. '-' |
| | | || 100n |
| | 500k +----||--+ |
'-' | || | |
| .-. === |
| | | GND |
| | | |
| '-'100k |
| | ||20n|
+---------+--------||---+
||

This configuration reduces the negative feedback and load on the
second inverter and steepens the approach to Vdd/2 at the input of the
first one.


Thanks. I wish I could do that but the layout, board fab and stuffing is
done :-(

Before we do a re-layout I will certainly look into this, or maybe throw
in my own transistor oscillator where I know I can get them under 10uA.
Another 40106 isn't an option because these sections must be independent
for safety reasons. While they did port the CD4000 to TSSOP it doesn't
come in singles.

You might also look at the variation where the feedback
capacitor is split into two capacitors in series to ground,
( a capacitive divider) each, half of the original
capacitance, and eliminate the 500k current limiting
capacitor to the first input. This puts a large capacitive
load on the second inverter, slowing its rise and fall time,
but actually lowers the second inverter's average supply
current by about a factor of 4, since only 1/4th the total
capacitance has to be charged up 10 volts and dumped each
cycle. But all that charge now has to be delivered during
the rise and fall time, instead of during the timing phase.
But it takes the clamp diodes out of the timing equation,
so that the oscillator is more temperature stable.

If you want to speed it up even a bit more, add a resistor
in series with the grounded capacitor of the output divider
that is about equal to the inverter output resistance.
This doesn't change the supply current consumed to charge
the divider, but speeds the transition of the first stage a
bit more. Whether that view is worth the climb depends on
how much faster that first stage is swinging.

Once this series of changes in implemented, the timing
waveform at the input if the first inverter can be made to
be an almost perfect ramp, instead of an exponential.
Constant rate of voltage change.