Chris Jones wrote:

Joerg wrote:


Hello Folks,

See the scope plot and excerpt from the ON Semi datasheet for the
CD4060. The blue trace is at the node RS/Rtc/Ctc, the yellow trace is at
pin 9 which is an output.

Why is there sag at the end of each phase? Rs is 500K and Rtc is 100K. I
mean, that shouldn't be any load to write home about even for a CD
series part.



From the polarity of the step in the waveform (which must be the same on
both ends of the capacitor for reasonable peak currents through the
capacitor), I would say that the yellow trace has to be Pin 10, not Pin 9.


Nope, yellow is pin 9.


Do you think that the sag might be due to the input voltage approaching the
threshold, and the finite gain of the gate? I would expect this to be
especially likely if it is an unbuffered version.


Yes, it seems to be the case. Beats me why they placed an unbuffered
inverter there, doesn't make much sense to me. Maybe batteries were
cheaper in the 70's when these chips were born ;-)

--
Regards, Joerg

http://www.analogconsultants.com