On Tue, 17 Jul 2007 08:18:20 -0700, "Harry Dellamano"
wrote:


"John Larkin" wrote in message
.. .
On Mon, 16 Jul 2007 18:53:07 -0700, "Harry Dellamano"
wrote:


"John Larkin" wrote in
message
...
On Mon, 16 Jul 2007 13:11:46 -0700, "Harry Dellamano"
wrote:


"John Larkin" wrote in
message
om...

With some decent code, this could measure capacitance (uF range, not
pFs), true esr, resistance, millivolts, possibly a useful range of
inductances. It could find shorted pcb traces and maybe plot diode
curves.

The dac is optional, and the adc might be inside the uP.

This is a stage 0 brainstorm. Of course you can find objections, but
I'd prefer improvements.

John


As JL points out this is a nice "sort of everything meter". To me it
even
looks like an AWG. I believe the main thrust of this project is to
design
a
ESR Meter with the best design trade offs to meet our testing needs. To
measure a wide range of ESR, hopefully to 1mR. If other applications
fall
out of the design then we have an even more viable product but we should
initially focus on ESR.

With a wide range of series capacity in the DUT we need to either apply
a
fast current step, maybe 10uS or a continuous drive of 100KHz or
higher
to
diminish the capacity effects from resistance. JL's meter is just too
slow
for this task.

My numbers aren't bad.

Suppose you bang a 1 uF cap at 100 KHz. Its reactance is 1.6 ohms. So
a dumb impedance meter won't resolve even 2 ohms of esr worth squat.
Push F up, and sooner or later L will get you.

Suppose I dump 100 mA into 1 uF in 1 us or so. The voltage will rise
0.1 volts per usec, so I could squeeze off maybe 3 samples before the
adc rails. If I extrapolate the slope back, I'd expect to be able to
resolve maybe 0.2 ohms of esr, and simultaneously measure the
capacitance to a couple of percent for free. And I can do calibrations
and algorithms that no dumb analog circuit can do.

So quit bitching and draw something better.

John
In your initial response to Win in this thread you stated numbers like
50uA, 1nF and 20mS slope sampling times. That sounds slow but easily
attainable with the schematic shown. Now you state 100mA, 1uF and maybe
10uS
slope sample times. That is more in line with my above statement but you
schematic switching 100mA on in less than 1.0uS sounds difficult.

I think I mentioned that it wouldn't make esr measurements on
low-value caps. Neither would a 100 KHz impedance meter. Dumping 100
mA in 1 usec shouldn't be difficult. The 50 uA was the low end of the
current range, the sort of thing you'd use for low value caps or diode
curves.

Extrapolating back the slope to get ESR sounds neat.

If I can digitize the charging slope every 10 usec, I get a *lot* more
information than measuring the simple impedance with a square wave of
the same period. I can tease out the components.

Some repulsive algorithms and calibrations would be needed, but that's
what software is for, to do repulsive things.

Not bitching, just trying to understand the master.
Cheers,
Harry



As I said, this was a possible starting point for a group design.
Group design means people should help, play with ideas, offer
alternates, improve things. So far, only one original schematic has
been posted, mine, and all the reactions have been skeptical.

I've always thought s.e.d. should do a for-real group design.

C'mon guys, quit whinin' and start designin'

John

Attached sketch allows much higher currents (10A) in the discharge mode and
both current and voltage slopes can be extraplated back to the switch
closure. Any clamping or leakage by the unit under test will be ignored.
Cheers,
Harry


Nice. That can digitize a slow charge and also nab a high-current
discharge, extending ESR measurments to smaller caps. To do it really
right, lead resistance will need to be removed, so the cap voltage has
to be (nearly) simultaneously sampled with the discharge current,
interleaved maybe, with more math!

What if you charge a cap to a known voltage and pulse-discharge it for
a bit, constant-current or constant-r, and measure the residual
voltage. That would also inferr ESR, but might suffer from dielectric
absorption errors.

Yup, something can definitely be done in the discharge path to improve
ESR resolution.

Maybe we could consider a DSP or FPGA, instead of a slower uP. High
sample rates could be interesting.

John