On Tue, 01 May 2007 13:02:01 -0400, John Popelish
wrote:
Joerg wrote:
John Popelish wrote:
(snip)
Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?
If you have a power plane over a ground plane you don't need 3-4 caps.
I don't think you can reasonably make that blanket statement without
analysis of the specific situation. For one thing the total
capacitance of the power and ground planes is probably less than the
capacitance of a single bypass capacitor; the stored charge is almost
negligible and most of it is too far away to do any good for
bypassing. The advantages of power and ground planes are significant
- low power distribution impedance, paths for signal return currents
directly under and/or over traces for controlled impedance routing -
but bypass capacitance is not one of them even if you use an expensive
thin core like Samina BC (.001" dielectric thickness).
That said, I have not run across a situation which required more than
one bypass cap per power/gnd pin pair - yet. Usually packages which
need a lot of bypassing have a lot of power and gnd pins. But I am
sure there are exceptions.
That's not the question. The question is "if you are going
to try taking the advice to use 3 or 4 capacitors to filter
a supply pin, how would you go about connecting them up?"
The only way to find an accurate answer to that question is with a
field solver. Lots of people have done this and published their
results, these results have been discussed in detail on the SI list
and in recent books on signal integrity.
Interestingly, one of the things found by the simulations is that many
manufacturers app notes are basically wild guesses (what worked for
their prototypes presumably), while some are based on actual analysis.
I looked at your layouts, but can't evaluate any of them since you did
not show the power and ground pins you are trying to bypass, and the
only important layout factor is the inductance between the bypass caps
and those pins. Some comments anyhow: I would try to avoid mounting
parts at 45 degrees without a really good reason. The length of path
between the bypass caps and the package ground pins is as important as
the path to the power pins - don't think of the ground plane as a
perfect zero volt reference, think of it as the other power plane.
Sometimes you can get closest to package power and ground pins on the
component side, sometimes on the other side, and sometimes you need to
compromise due to other routing constraints, but low bypass inductance
should be a very high routing priority for high speed parts. Keep in
mind that the main purpose of bypassing is to keep the power supply
voltage at the device pins within limits on the worst case transient;
find out what that transient is and design to accomodate it.
You might want to take a look at Doug Brooks Bypass Capacitance
Impedance Calculator at
http://www.ultracad.com/calc.htm for a
simplified bypass cap analysis (well short of a field solver but way
better than guessing).
Regards,
Glen