This graphic is something I drew after thinking about the
multi 0102 SMT bypass capacitor thread in
sci.electronics.design. Is there a better way to bring a
supply in (from the top) past several SMT bypass capacitors?
The vias on both sides are to the ground layer.

John Popelish wrote:

This graphic is something I drew after thinking about the multi 0102 SMT
bypass capacitor thread in sci.electronics.design. Is there a better
way to bring a supply in (from the top) past several SMT bypass
capacitors? The vias on both sides are to the ground layer.

------------------------------------------------------------------------


Yep, by having the vias to the ground plane in the pads. But be prepared
for some eggs and tomatoes flying, from the production folks. At least
make the ground traces there wider, a little "mini plane".

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
John Popelish wrote:

This graphic is something I drew after thinking about the multi 0102
SMT bypass capacitor thread in sci.electronics.design. Is there a
better way to bring a supply in (from the top) past several SMT bypass
capacitors? The vias on both sides are to the ground layer.

------------------------------------------------------------------------


Yep, by having the vias to the ground plane in the pads. But be prepared
for some eggs and tomatoes flying,

Not familiar with that technical expression.

from the production folks. At least
make the ground traces there wider, a little "mini plane".

I don't see the value in a mini plane connected to the
buried plane with vias, but I can see that using a wider
trace that surrounds 3 sides of the capacitor ground pad
would lower the inductance of that path to the via.

A lot of the details of this sort of layout depend on the
rules for the PCB process (minimum solder mask width,
minimum distance between via and pad, etc.)

John Popelish wrote:

Joerg wrote:

John Popelish wrote:

This graphic is something I drew after thinking about the multi 0102
SMT bypass capacitor thread in sci.electronics.design. Is there a
better way to bring a supply in (from the top) past several SMT
bypass capacitors? The vias on both sides are to the ground layer.

------------------------------------------------------------------------


Yep, by having the vias to the ground plane in the pads. But be
prepared for some eggs and tomatoes flying,


Not familiar with that technical expression.


A via inside the footprint of a part is often frowned upon but it's been
done. It can mess with the thermal profile of the solder process.


from the production folks. At least make the ground traces there
wider, a little "mini plane".


I don't see the value in a mini plane connected to the buried plane with
vias, but I can see that using a wider trace that surrounds 3 sides of
the capacitor ground pad would lower the inductance of that path to the
via.


A mini plane lowers the inductance from the footprint area to the next
via but the effect is quite marginal. Much more important is that the
distance to the next via is as close to zero as you can get it.


A lot of the details of this sort of layout depend on the rules for the
PCB process (minimum solder mask width, minimum distance between via and
pad, etc.)


Yes. That's one reason I don't do layouts and probably never will. It is
a full time job to stay abreast of all that and my layouter does a very
good job. He can tell me off the top of his head whether something flies
or not, and often comes back with good alternative suggestions.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
John Popelish wrote:

Joerg wrote:

Yep, by having the vias to the ground plane in the pads. But be
prepared for some eggs and tomatoes flying,


Not familiar with that technical expression.


A via inside the footprint of a part is often frowned upon but it's been
done. It can mess with the thermal profile of the solder process.
(snip)

I was referring to "eggs and tomatoes flying". :-)
I have no vias inside the pads in my graphic. The black
lines are the part (min and max size) and pads. the red
lines are the traces and vias.

Here is a version with wider ground traces and the vias
moved right up to the pads.

John Popelish wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:


Yep, by having the vias to the ground plane in the pads. But be
prepared for some eggs and tomatoes flying,



Not familiar with that technical expression.


A via inside the footprint of a part is often frowned upon but it's
been done. It can mess with the thermal profile of the solder process.

(snip)

I was referring to "eggs and tomatoes flying". :-)
I have no vias inside the pads in my graphic. The black lines are the
part (min and max size) and pads. the red lines are the traces and vias.

Here is a version with wider ground traces and the vias moved right up
to the pads.


If you can't have vias in the pads that should do a pretty good job. It
depends on what you want to filter. Many times it's to provide a low
impedance node at the pin or to avoid EMI from the chip leaking out.
Then I usually place a 0.1uF and a 4700pF or so "head to head". That
makes for the shortest distance of either one to the supply pin.

Bottomline the best line of defense is IMHO a nice fat power plane that
capacitively couples to a full ground plane. Then you can sprinkle the
0.1uF caps with more tolerance and can forego smaller values because the
plane to plane capacitance takes care of the really high noise spectra.

Of course I realize that the mere mention of a ground plane might
trigger a whole new ground philisophy thread. Well, considering the
current mess on s.e.d., maybe not this time.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:

If you can't have vias in the pads that should do a pretty good job. It
depends on what you want to filter. Many times it's to provide a low
impedance node at the pin or to avoid EMI from the chip leaking out.
Then I usually place a 0.1uF and a 4700pF or so "head to head". That
makes for the shortest distance of either one to the supply pin.

I have not built anything that required more than a single
bypass capacitor at each power pin.

Bottomline the best line of defense is IMHO a nice fat power plane that
capacitively couples to a full ground plane. Then you can sprinkle the
0.1uF caps with more tolerance and can forego smaller values because the
plane to plane capacitance takes care of the really high noise spectra.

Of course I realize that the mere mention of a ground plane might
trigger a whole new ground philisophy thread. Well, considering the
current mess on s.e.d., maybe not this time.

I am very happy to have a ground plane, but this thread was
prompted by a thread in sci.electronics.design about advice
to use multiple capacitors (more than 2 specific values) as
bypass for some demanding application. I am just
hypothesizing about how I would actually do that, if I could
be convinced that it might accomplish something. The small
size of 0201 SMT parts also limits the possibilities.

John Popelish wrote:

Joerg wrote:

If you can't have vias in the pads that should do a pretty good job.
It depends on what you want to filter. Many times it's to provide a
low impedance node at the pin or to avoid EMI from the chip leaking
out. Then I usually place a 0.1uF and a 4700pF or so "head to head".
That makes for the shortest distance of either one to the supply pin.


I have not built anything that required more than a single bypass
capacitor at each power pin.


I did but that was where I could not have a wide enough supply plane. An
AD converter. For the heck I took out the 4700pF cap and sure enough the
internal clock feedthrough became noticeably worse.


Bottomline the best line of defense is IMHO a nice fat power plane
that capacitively couples to a full ground plane. Then you can
sprinkle the 0.1uF caps with more tolerance and can forego smaller
values because the plane to plane capacitance takes care of the really
high noise spectra.

Of course I realize that the mere mention of a ground plane might
trigger a whole new ground philisophy thread. Well, considering the
current mess on s.e.d., maybe not this time.


I am very happy to have a ground plane, but this thread was prompted by
a thread in sci.electronics.design about advice to use multiple
capacitors (more than 2 specific values) as bypass for some demanding
application. I am just hypothesizing about how I would actually do
that, if I could be convinced that it might accomplish something. The
small size of 0201 SMT parts also limits the possibilities.


In that thread it seemed like a consultant was going a wee bit overboard
by simulating something to death. Best is to just lay it out and try. I
bet that company would have already saved a ton of money that way.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit overboard
by simulating something to death. Best is to just lay it out and try.
(snip)

Yes, but lay it out, how? It didn't sound like they were
getting advice on layout. I was trying to imagine the
choices and which were better than others.

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it out
and try.

(snip)

Yes, but lay it out, how? It didn't sound like they were getting advice
on layout. I was trying to imagine the choices and which were better
than others.


Oh, just the usual. Full ground plane, nice fat power plane of at least
a few square inches or preferably also full. If you have a hotrod noise
sensitive circuit you can't be skimpy on the number of layers. They
seemed to not be getting advice on layout from their consultant but they
should have. Later when it works they can then try to squish out the
last penny by cutting down a couple of layers. But that is not easy.

Heck, I can't even find that thread on s.e.d. anymore after some
knuckleheads showed up there.

--
Regards, Joerg

http://www.analogconsultants.com

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it out
and try.

(snip)

Yes, but lay it out, how? It didn't sound like they were getting advice
on layout. I was trying to imagine the choices and which were better
than others.


Ok, found the OP's post in that grounding thread and asked him what came
of all that so far. If they are still philosophying maybe it's time to
cut to the chase and just lay it out. T'is what my layouter is doing
right now with a pretty itchy laser loop design. Nanovolt stuff. We
could have kept on theorizing but that wouldn't get us anywhere.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.

(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which were
better than others.


Ok, found the OP's post in that grounding thread and asked him what came
of all that so far. If they are still philosophying maybe it's time to
cut to the chase and just lay it out. T'is what my layouter is doing
right now with a pretty itchy laser loop design. Nanovolt stuff. We
could have kept on theorizing but that wouldn't get us anywhere.

Okay, humor me. Assume you were actually going to try to
put 3 or 4 capacitors on a power pin. It is assumed that
there are at least a power and ground plane buried under the
chip. How would you arrange 3 or 4 capacitor around a power
pin to provide the lowest impedance over the broadest band
of frequencies if space were not a problem? What if you had
to route lots of traces past this monstrosity?

Am I the only person who lays awake at night picturing
little blocks and vias interconnected by traces in various
ways trying to imagine how each of the variations differs in
its resonances? ;-)

You should see some of the other, stranger versions I came
up with. For some reason, the art of PCB layout fascinates me.

On Mon, 30 Apr 2007 18:57:58 -0400, John Popelish
wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit overboard
by simulating something to death. Best is to just lay it out and try.
(snip)

Just lay it out and try it works most of the time with the slow
signals in many uP based products, but I would not want to buy a
computer designed that way.

Yes, but lay it out, how? It didn't sound like they were
getting advice on layout. I was trying to imagine the
choices and which were better than others.

This matter has been discussed endlessly on the signal integrity list,
ref pasted below if you want to search the archives. IMO bypass caps
are best selected to meet some particular impedance level at a
frequency which depends where you are in the power distribution. The
highest frequencies can only be dealt with on chip because of wirebond
inductance, then the next lower frequencies can only be dealt with in
the package, then when you get to the board the package inductance
means you can only effectively decouple the IC up to a few hundred MHz
from there. So you want to get as much capacitance as you need with
the least possible inductance, where the inductance will likely be the
important limiting factor. Use the smallest cap package you can for
lowest inductance, and the largest available capacitance in that
package. Using less than the maximum capacitance in the selected
package for bypass makes no sense, do the math. Get the caps as close
to the power pin as you can, pwr/gnd loop area as small as you can,
and get all the gory details available for free at SI archives:

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Glen Walpert wrote:
(snip)
This matter has been discussed endlessly on the signal integrity list,
ref pasted below if you want to search the archives.
(snip)
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For help:
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or at our remote archives:
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Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu

Thanks. I'll have a look around.

John Popelish wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.


(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which were
better than others.



Ok, found the OP's post in that grounding thread and asked him what
came of all that so far. If they are still philosophying maybe it's
time to cut to the chase and just lay it out. T'is what my layouter is
doing right now with a pretty itchy laser loop design. Nanovolt stuff.
We could have kept on theorizing but that wouldn't get us anywhere.


Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.
One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.

As to arrangement: We've done just that on a new project, or rather, my
layouter has. He placed all bypass caps on the solder side, via'd smack
dab into the pin pads.


Am I the only person who lays awake at night picturing little blocks and
vias interconnected by traces in various ways trying to imagine how each
of the variations differs in its resonances? ;-)


Maybe :-)

I've never lost any sleep about that. I did lose sleep over availability
of some parts though, or after that chemical plant in Asia blew up and
we could not buy Z5U caps anywhere for months. But mostly I lay awake
thinking about the workers there that got hurt.


You should see some of the other, stranger versions I came up with. For
some reason, the art of PCB layout fascinates me.


Hmm, I really don't see much art in bypassing. The artsy stuff comes
into play when you do zero-$ tapped inductors or RF couplers as artwork.
That is the only time I actually do part of a layout.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
John Popelish wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.


(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which
were better than others.



Ok, found the OP's post in that grounding thread and asked him what
came of all that so far. If they are still philosophying maybe it's
time to cut to the chase and just lay it out. T'is what my layouter
is doing right now with a pretty itchy laser loop design. Nanovolt
stuff. We could have kept on theorizing but that wouldn't get us
anywhere.


Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.
One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.


But that's not necessarily a big help at lower frequency, and can even
be harmful sometimes.

I had a weird bug once in a circuit that had three (nominally identical)
high gain phase sensitive detectors. Two of them were well-behaved, but
the third had an obscenely large offset at the output.

It turned out to be *one pad* sitting over a noisy power plane that was
bouncing up and down by ~50 mV at the signal frequency of about 100 kHz.
100 femtofarads or thereabouts was all it took. I eventually patched
it by putting 10 ohms+100 uF decoupling on the switching element that
was making the power bounce.

Cheers,

Phil Hobbs

Joerg wrote:
John Popelish wrote:
(snip)
Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.

That's not the question. The question is "if you are going
to try taking the advice to use 3 or 4 capacitors to filter
a supply pin, how would you go about connecting them up?"

Instead of answering the question, you are giving advice. I
appreciate your experience, but it doesn't answer the
(possibly silly) question.

One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.

As to arrangement: We've done just that on a new project, or rather, my
layouter has. He placed all bypass caps on the solder side, via'd smack
dab into the pin pads.

Sorry, I can't picture "smack dab". I can picture one or
more vias passing through the power plane and connecting to
the pin pad, with several capacitors clustered around that
through connection under the pin pad. I have attached some
possible examples.

(snip)
You should see some of the other, stranger versions I came up with.
For some reason, the art of PCB layout fascinates me.


Hmm, I really don't see much art in bypassing. The artsy stuff comes
into play when you do zero-$ tapped inductors or RF couplers as artwork.
That is the only time I actually do part of a layout.

Maybe you should start a thread with some educational clips.
My best layout features, lately have been shielding and
guarding involving multiple layers. I had two socket
mounted photo diodes, one above the positive side of the
supply and one above the negative side of the supply (split
plane) all over a ground plane, with the amplifiers on the
other side, over the ground plane.

I had to keep the capacitance between the diode output pins
and those two supply planes in the fempto farads, so that I
could amplify the difference of their two outputs without
seeing any differential contamination from the supply
ripple. Took me a couple tries to get it right and involved
concentric features on all 4 layers.

I forgot to mention that the black squares around those last
cases are a .1" by .1" size reference.

Phil Hobbs wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.



(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which
were better than others.




Ok, found the OP's post in that grounding thread and asked him what
came of all that so far. If they are still philosophying maybe it's
time to cut to the chase and just lay it out. T'is what my layouter
is doing right now with a pretty itchy laser loop design. Nanovolt
stuff. We could have kept on theorizing but that wouldn't get us
anywhere.



Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange
3 or 4 capacitor around a power pin to provide the lowest impedance
over the broadest band of frequencies if space were not a problem?
What if you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.
One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.


But that's not necessarily a big help at lower frequency, and can even
be harmful sometimes.

I had a weird bug once in a circuit that had three (nominally identical)
high gain phase sensitive detectors. Two of them were well-behaved, but
the third had an obscenely large offset at the output.

It turned out to be *one pad* sitting over a noisy power plane that was
bouncing up and down by ~50 mV at the signal frequency of about 100 kHz.
100 femtofarads or thereabouts was all it took. I eventually patched
it by putting 10 ohms+100 uF decoupling on the switching element that
was making the power bounce.


50mV is a whole lot of noise at 100kHz. Were you guys a bit skimpy on
bypass caps? I have a (huge) laser + photodiode board in layout right
now and it's got oodles of 0.1uF, plus 47uF caps sprinkled about.

--
Regards, Joerg

http://www.analogconsultants.com

John Popelish wrote:

Joerg wrote:

John Popelish wrote:

(snip)

Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange
3 or 4 capacitor around a power pin to provide the lowest impedance
over the broadest band of frequencies if space were not a problem?
What if you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.


That's not the question. The question is "if you are going to try
taking the advice to use 3 or 4 capacitors to filter a supply pin, how
would you go about connecting them up?"


Pretty much like the stars you have shown. A stretched out path as
you've had in your first post adds inductance and that is not good for
stability of the VCC pin. If the chip has lots of current swings inside
it'll "self pollute". So you star architecture is IMHO better. I like
the one in the lower left is best. The caps are close together and the
vias are (almost) shortest path although not as short as through the pads.

But, as said before, I would not take this advice :-)


Instead of answering the question, you are giving advice. I appreciate
your experience, but it doesn't answer the (possibly silly) question.


Ok, sorry. But if someone were to make a similar suggestion of using a
concoction of caps in lieu of a plane there would be some red flags
going up in my head ;-)


One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.

As to arrangement: We've done just that on a new project, or rather,
my layouter has. He placed all bypass caps on the solder side, via'd
smack dab into the pin pads.


Sorry, I can't picture "smack dab". I can picture one or more vias
passing through the power plane and connecting to the pin pad, with
several capacitors clustered around that through connection under the
pin pad. I have attached some possible examples.


That's how we are doing it in the current layout except that from the
four caps shown on the lower left drawing there will only be one ;-)

(snip)

You should see some of the other, stranger versions I came up with.
For some reason, the art of PCB layout fascinates me.



Hmm, I really don't see much art in bypassing. The artsy stuff comes
into play when you do zero-$ tapped inductors or RF couplers as
artwork. That is the only time I actually do part of a layout.


Maybe you should start a thread with some educational clips. My best
layout features, lately have been shielding and guarding involving
multiple layers. I had two socket mounted photo diodes, one above the
positive side of the supply and one above the negative side of the
supply (split plane) all over a ground plane, with the amplifiers on the
other side, over the ground plane.

I had to keep the capacitance between the diode output pins and those
two supply planes in the fempto farads, so that I could amplify the
difference of their two outputs without seeing any differential
contamination from the supply ripple. Took me a couple tries to get it
right and involved concentric features on all 4 layers.


Yes, guard rings are also part of the artsy side in layout. But you did
the right thing, instead of simulating it to death you pushed forward
and did it. Else you might still be mired in SPICE files right now...

I'd love to do educational clips. Problem is, these are quite hot
designs and the shroud of secrecy is tight. The agreements almost spell
out the size of the bullet that will be used in case I snitch.

Education is, for me, the nicest part about consulting. Sometimes you
get to re-introduce long forgotten techniques and jaws drop. The best
recent experience was a short speech about how to use a Smith Chart. As
an example I took the very problem the client was trying to solve via a
sizeable set of Matlab equations. In about five minutes we had the
inductor values, cables length and the whole nine yards done. Ready to
order parts. Could have been one minute but I wanted to explain what
every step did. That's when the jaws really dropped, mainly because they
thought Smith Charts are something for old farts.

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
Phil Hobbs wrote:
Joerg wrote:
snip
If you have a power plane over a ground plane you don't need 3-4
caps. One or two at the most will be fine because the planes take
care of everything 100MHz. So, if something is this critical I
always make sure there is a power plane.


But that's not necessarily a big help at lower frequency, and can even
be harmful sometimes.

I had a weird bug once in a circuit that had three (nominally
identical) high gain phase sensitive detectors. Two of them were
well-behaved, but the third had an obscenely large offset at the output.

It turned out to be *one pad* sitting over a noisy power plane that
was bouncing up and down by ~50 mV at the signal frequency of about
100 kHz. 100 femtofarads or thereabouts was all it took. I
eventually patched it by putting 10 ohms+100 uF decoupling on the
switching element that was making the power bounce.


50mV is a whole lot of noise at 100kHz. Were you guys a bit skimpy on
bypass caps? I have a (huge) laser + photodiode board in layout right
now and it's got oodles of 0.1uF, plus 47uF caps sprinkled about.


I was the culprit. That plane was a 12V supply from a wall wart, and
was just running a bit of insensitive stuff like RS-232 comms and the
chopped LED light source that was causing the ripple. The low noise
supply was derived from it using a capacitance multiplier, which caused
absolutely no issues (~90-100 dB rejection, pretty amazing for a
MMBT3904). All those 47-uf caps would have cost a lot...the idea was to
have a head tracker that was supposed to cost $10 in quantity, minus the
wall wart and serial cable. Getting rid of the noise at the source was
cheaper than fixing it afterwards, but a small layout change would have
worked just as well.

The thing was, I thought I had it right at the time--the power plane was
split, half being the noisy-12V and half the quiet-11.3V from the cap
multiplier. All the analog stuff was routed on top of the ground plane
or over the quiet supply plane, except for that one lonely 0.7 mm square
pad.

Cheers,

Phil Hobbs

Phil Hobbs wrote:
(snip)
The thing was, I thought I had it right at the time--the power plane was
split, half being the noisy-12V and half the quiet-11.3V from the cap
multiplier. All the analog stuff was routed on top of the ground plane
or over the quiet supply plane, except for that one lonely 0.7 mm square
pad.

What a story. This is the kind of thing that causes me to
put up screen wall paper of any layout in progress, so when
my mind is blank, my subconscious can wonder over the layout
and raise red flags. By the time the board is produced, I
have no need of either a schematic or a layout diagram. I
am familiar with every trace.

Of course, it means that the layout people get sick of
hearing from me about details.

Phil Hobbs wrote:

Joerg wrote:

Phil Hobbs wrote:

Joerg wrote:

snip

If you have a power plane over a ground plane you don't need 3-4
caps. One or two at the most will be fine because the planes take
care of everything 100MHz. So, if something is this critical I
always make sure there is a power plane.


But that's not necessarily a big help at lower frequency, and can
even be harmful sometimes.

I had a weird bug once in a circuit that had three (nominally
identical) high gain phase sensitive detectors. Two of them were
well-behaved, but the third had an obscenely large offset at the output.

It turned out to be *one pad* sitting over a noisy power plane that
was bouncing up and down by ~50 mV at the signal frequency of about
100 kHz. 100 femtofarads or thereabouts was all it took. I
eventually patched it by putting 10 ohms+100 uF decoupling on the
switching element that was making the power bounce.


50mV is a whole lot of noise at 100kHz. Were you guys a bit skimpy on
bypass caps? I have a (huge) laser + photodiode board in layout right
now and it's got oodles of 0.1uF, plus 47uF caps sprinkled about.


I was the culprit. That plane was a 12V supply from a wall wart, and
was just running a bit of insensitive stuff like RS-232 comms and the
chopped LED light source that was causing the ripple. The low noise
supply was derived from it using a capacitance multiplier, which caused
absolutely no issues (~90-100 dB rejection, pretty amazing for a
MMBT3904). All those 47-uf caps would have cost a lot...the idea was to
have a head tracker that was supposed to cost $10 in quantity, minus the
wall wart and serial cable. Getting rid of the noise at the source was
cheaper than fixing it afterwards, but a small layout change would have
worked just as well.


Those bootstrapped caps really work. This time I went a step further and
sprung for a BCX70K instead of the 3904. Only a fraction of a cent more
but really low noise. John Larkin had suggested that transistor a while ago.


The thing was, I thought I had it right at the time--the power plane was
split, half being the noisy-12V and half the quiet-11.3V from the cap
multiplier. All the analog stuff was routed on top of the ground plane
or over the quiet supply plane, except for that one lonely 0.7 mm square
pad.


Oops. Probably like trying to maintain a cell phone conversation during
a heavy metal concert ;-)

--
Regards, Joerg

http://www.analogconsultants.com

John Popelish wrote:

Phil Hobbs wrote:
(snip)

The thing was, I thought I had it right at the time--the power plane
was split, half being the noisy-12V and half the quiet-11.3V from the
cap multiplier. All the analog stuff was routed on top of the ground
plane or over the quiet supply plane, except for that one lonely 0.7
mm square pad.


What a story. This is the kind of thing that causes me to put up screen
wall paper of any layout in progress, so when my mind is blank, my
subconscious can wonder over the layout and raise red flags. By the
time the board is produced, I have no need of either a schematic or a
layout diagram. I am familiar with every trace.


Gerber viewers cause less cutting of trees ;-)

Your suggestion is actually a good one. If I find a decently priced
Gerber viewer with transparent layer view maybe I could capture a screnn
and use each chunk as a screen saver for a while. Kind of gaze at it.


Of course, it means that the layout people get sick of hearing from me
about details.


I am lucky. Found a layouter who is also EE and does designs. Things is,
sometimes all I have to tell him is that this, that and the other thing
is "RF hot" and he does it right. It takes only few words and he'll
understand how a particular circuit works. Can't say that about recent
grads from universities :-(

--
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:

Gerber viewers cause less cutting of trees ;-)

Your suggestion is actually a good one. If I find a decently priced
Gerber viewer with transparent layer view maybe I could capture a screnn
and use each chunk as a screen saver for a while. Kind of gaze at it.
(snip)

There are several good, free Gerber viewers (that don't
allow file saves) on the net. I think this is the one I use
at work:
http://www.graphicode.com/pages/prevue.cfm

John Popelish wrote:
Joerg wrote:

Gerber viewers cause less cutting of trees ;-)



Your suggestion is actually a good one. If I find a decently priced
Gerber viewer with transparent layer view maybe I could capture a
screnn and use each chunk as a screen saver for a while. Kind of gaze
at it.

(snip)

There are several good, free Gerber viewers (that don't allow file
saves) on the net. I think this is the one I use at work:
http://www.graphicode.com/pages/prevue.cfm


That's the one I also use, GC-Prevue. But it doesn't allow transparent
layers. Only solid colors which doesn't make much sense to me. IOW you
must hide/unhide all the time to see where a traces is running under
another and where they connect. I remember back in Europe I had a DOS
program that could already do that, late 80's early 90's or so. It was
from France and I had to get used to a user interface in French but that
was much easier than all this mouse clicking.

--
Regards, Joerg

http://www.analogconsultants.com

On Tue, 01 May 2007 13:02:01 -0400, John Popelish
wrote:

Joerg wrote:
John Popelish wrote:
(snip)
Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.

I don't think you can reasonably make that blanket statement without
analysis of the specific situation. For one thing the total
capacitance of the power and ground planes is probably less than the
capacitance of a single bypass capacitor; the stored charge is almost
negligible and most of it is too far away to do any good for
bypassing. The advantages of power and ground planes are significant
- low power distribution impedance, paths for signal return currents
directly under and/or over traces for controlled impedance routing -
but bypass capacitance is not one of them even if you use an expensive
thin core like Samina BC (.001" dielectric thickness).

That said, I have not run across a situation which required more than
one bypass cap per power/gnd pin pair - yet. Usually packages which
need a lot of bypassing have a lot of power and gnd pins. But I am
sure there are exceptions.

That's not the question. The question is "if you are going
to try taking the advice to use 3 or 4 capacitors to filter
a supply pin, how would you go about connecting them up?"

The only way to find an accurate answer to that question is with a
field solver. Lots of people have done this and published their
results, these results have been discussed in detail on the SI list
and in recent books on signal integrity.

Interestingly, one of the things found by the simulations is that many
manufacturers app notes are basically wild guesses (what worked for
their prototypes presumably), while some are based on actual analysis.

I looked at your layouts, but can't evaluate any of them since you did
not show the power and ground pins you are trying to bypass, and the
only important layout factor is the inductance between the bypass caps
and those pins. Some comments anyhow: I would try to avoid mounting
parts at 45 degrees without a really good reason. The length of path
between the bypass caps and the package ground pins is as important as
the path to the power pins - don't think of the ground plane as a
perfect zero volt reference, think of it as the other power plane.
Sometimes you can get closest to package power and ground pins on the
component side, sometimes on the other side, and sometimes you need to
compromise due to other routing constraints, but low bypass inductance
should be a very high routing priority for high speed parts. Keep in
mind that the main purpose of bypassing is to keep the power supply
voltage at the device pins within limits on the worst case transient;
find out what that transient is and design to accomodate it.

You might want to take a look at Doug Brooks Bypass Capacitance
Impedance Calculator at http://www.ultracad.com/calc.htm for a
simplified bypass cap analysis (well short of a field solver but way
better than guessing).

Regards,
Glen

Glen Walpert wrote:

I looked at your layouts, but can't evaluate any of them since you did
not show the power and ground pins you are trying to bypass, and the
only important layout factor is the inductance between the bypass caps
and those pins.

In the first case the linear one) the top center via is the
connection to the power plane, and the rest are connections
to the ground plane. The center trace out the bottom is
what connects to the chip pad. Caps and chip on the same side.

In the other cases, the center via(s) connect to both the
power plane and the pad to the chip pin on the other side of
the board. The peripheral vias connect to the ground plane.
I would not use thermals on any of these, not so much
because of worries about resistance increase, but to reduce
the size of holes in the planes.

Some comments anyhow: I would try to avoid mounting
parts at 45 degrees without a really good reason.

Agreed.

The length of path
between the bypass caps and the package ground pins is as important as
the path to the power pins - don't think of the ground plane as a
perfect zero volt reference, think of it as the other power plane.
Sometimes you can get closest to package power and ground pins on the
component side, sometimes on the other side, and sometimes you need to
compromise due to other routing constraints, but low bypass inductance
should be a very high routing priority for high speed parts. Keep in
mind that the main purpose of bypassing is to keep the power supply
voltage at the device pins within limits on the worst case transient;
find out what that transient is and design to accomodate it.

All good.

You might want to take a look at Doug Brooks Bypass Capacitance
Impedance Calculator at http://www.ultracad.com/calc.htm for a
simplified bypass cap analysis (well short of a field solver but way
better than guessing).

Thanks.

Regards,
Glen

On Wed, 02 May 2007 10:36:36 -0400, John Popelish
wrote:

Glen Walpert wrote:

I looked at your layouts, but can't evaluate any of them since you did
not show the power and ground pins you are trying to bypass, and the
only important layout factor is the inductance between the bypass caps
and those pins.

In the first case the linear one) the top center via is the
connection to the power plane, and the rest are connections
to the ground plane. The center trace out the bottom is
what connects to the chip pad. Caps and chip on the same side.

OK, I guess that should have been obvious. The tighter of these two
layouts would theoretically be a tad better due to lower inductance in
the ground connections. But both of these have only a single power
via vice 6 ground vias, arranged more as a power supply filter than as
bypassing, where I would expect to see equal numbers of power and
ground vias as close together as your layout rules allow. The primary
layout goal here being to keep the total loop area between your caps
and part power and ground pins as small as practical. You seem to
have more trace distance than necessary between the power plane and
the component, and you seem to be treating the power connection
differently than ground connection which is not shown but presumably
is close by and connected to your bypass caps through the ground plane
with a single via near the pin. I think a more symnetric arrangement
WRT power and ground would be better even if it means spreading the
caps out a bit more. Not to say that your layouts would not work as
shown.

In the other cases, the center via(s) connect to both the
power plane and the pad to the chip pin on the other side of
the board. The peripheral vias connect to the ground plane.
I would not use thermals on any of these, not so much
because of worries about resistance increase, but to reduce
the size of holes in the planes.

There are similar asymetries here, and I wonder if you could not
accomplish the same task with all caps having the same orientation,
two vias per cap preferably on the sides rather than the ends so that
the power and gnd vias are close for minimum loop area, and located as
close to centered between IC power and gnd pins as your layout
permits.

Using a direct trace from the caps to IC vice having the caps and IC
pins both connected to the planes with separate vias (as your posted
layouts do with ground) might not make much difference in total
inductance between caps and part pins, and eliminating the direct
trace might make layout easier in some cases.

When your bypass caps are this small even a sub-optimal layout has a
rather small loop area (low inductance) and I suspect that somewhat
less care in keeping loop areas small would be required than when
using larger parts for the same job.

I plan to start layout of my first design using 0201 parts in a few
weeks. 01005 can't be far behind. We live in interesting times, eh?

Regards,
Glen