Joerg wrote:
John Popelish wrote:

Joerg wrote:

John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.


(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which
were better than others.



Ok, found the OP's post in that grounding thread and asked him what
came of all that so far. If they are still philosophying maybe it's
time to cut to the chase and just lay it out. T'is what my layouter
is doing right now with a pretty itchy laser loop design. Nanovolt
stuff. We could have kept on theorizing but that wouldn't get us
anywhere.


Okay, humor me. Assume you were actually going to try to put 3 or 4
capacitors on a power pin. It is assumed that there are at least a
power and ground plane buried under the chip. How would you arrange 3
or 4 capacitor around a power pin to provide the lowest impedance over
the broadest band of frequencies if space were not a problem? What if
you had to route lots of traces past this monstrosity?


If you have a power plane over a ground plane you don't need 3-4 caps.
One or two at the most will be fine because the planes take care of
everything 100MHz. So, if something is this critical I always make
sure there is a power plane.


But that's not necessarily a big help at lower frequency, and can even
be harmful sometimes.

I had a weird bug once in a circuit that had three (nominally identical)
high gain phase sensitive detectors. Two of them were well-behaved, but
the third had an obscenely large offset at the output.

It turned out to be *one pad* sitting over a noisy power plane that was
bouncing up and down by ~50 mV at the signal frequency of about 100 kHz.
100 femtofarads or thereabouts was all it took. I eventually patched
it by putting 10 ohms+100 uF decoupling on the switching element that
was making the power bounce.

Cheers,

Phil Hobbs