Joerg wrote:
John Popelish wrote:

Joerg wrote:

In that thread it seemed like a consultant was going a wee bit
overboard by simulating something to death. Best is to just lay it
out and try.

(snip)

Yes, but lay it out, how? It didn't sound like they were getting
advice on layout. I was trying to imagine the choices and which were
better than others.


Ok, found the OP's post in that grounding thread and asked him what came
of all that so far. If they are still philosophying maybe it's time to
cut to the chase and just lay it out. T'is what my layouter is doing
right now with a pretty itchy laser loop design. Nanovolt stuff. We
could have kept on theorizing but that wouldn't get us anywhere.

Okay, humor me. Assume you were actually going to try to
put 3 or 4 capacitors on a power pin. It is assumed that
there are at least a power and ground plane buried under the
chip. How would you arrange 3 or 4 capacitor around a power
pin to provide the lowest impedance over the broadest band
of frequencies if space were not a problem? What if you had
to route lots of traces past this monstrosity?

Am I the only person who lays awake at night picturing
little blocks and vias interconnected by traces in various
ways trying to imagine how each of the variations differs in
its resonances? ;-)

You should see some of the other, stranger versions I came
up with. For some reason, the art of PCB layout fascinates me.