View Single Post
  #7   Report Post  
Posted to alt.binaries.schematics.electronic
John Popelish John Popelish is offline
external usenet poster
 
Posts: 172
Default SMT layout for multi capacitor bypass

Joerg wrote:

If you can't have vias in the pads that should do a pretty good job. It
depends on what you want to filter. Many times it's to provide a low
impedance node at the pin or to avoid EMI from the chip leaking out.
Then I usually place a 0.1uF and a 4700pF or so "head to head". That
makes for the shortest distance of either one to the supply pin.


I have not built anything that required more than a single
bypass capacitor at each power pin.

Bottomline the best line of defense is IMHO a nice fat power plane that
capacitively couples to a full ground plane. Then you can sprinkle the
0.1uF caps with more tolerance and can forego smaller values because the
plane to plane capacitance takes care of the really high noise spectra.

Of course I realize that the mere mention of a ground plane might
trigger a whole new ground philisophy thread. Well, considering the
current mess on s.e.d., maybe not this time.


I am very happy to have a ground plane, but this thread was
prompted by a thread in sci.electronics.design about advice
to use multiple capacitors (more than 2 specific values) as
bypass for some demanding application. I am just
hypothesizing about how I would actually do that, if I could
be convinced that it might accomplish something. The small
size of 0201 SMT parts also limits the possibilities.